Re: Caching on Intel Chips

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Article #13

#13

From: David C. Barber
Date: Wed, 28 Oct 1992 07:09

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In <1992Oct22.054643.27802@exucom.com> cyberman@exucom.com (Stephen R. Phillips) writes:

>Thier I860 chipset uses seperate chaches.
>They may have a problem with the using I and D caches since with a
>CISC processor thing get more convoluted :)

>Cyberman/Stephen

You are right about seperate I & D caches being a problem on many
CISC machines.  You didn't give the main reason though:  CISC machines
(like x86 series) can dynamically programatically alter their code by
way of data writes that have to be able to find their way into the
instruction cache.

Without change,                         *David Barber*
   nothing can ever get better.            @}-->----

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References: <1992Oct21.175835.2971@cs.mcgill.ca> <1992Oct22.054643.27802@exucom.com>

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Newsgroups: comp.sys.intel
Path: arc1-ca.pugleaf.net!sparky!uunet!sun-barr!ames!agate!dog.ee.lbl.gov!news!nosc!crash!dbarber
From: dbarber@crash.cts.com (David C. Barber)
Subject: Re: Caching on Intel Chips
Organization: CTS Network Services (crash, ctsnet), El Cajon, CA
Date: 28 Oct 92 07:09:28 GMT
Message-ID: <dbarber.720256168@crash.cts.com>
References: <1992Oct21.175835.2971@cs.mcgill.ca> <1992Oct22.054643.27802@exucom.com>
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