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Article #1467

Re: Parity on iAPX x86 chips

#1467
From: Michael Davidson
Date: Tue, 12 Jan 1993 19:58
16 lines
1251 bytes
storm@cs.mcgill.ca (Marc WANDSCHNEIDER) writes:

>I've noticed that most of the x86 chips I have programmed have a Parity
>bit.  I was just wondering if they actually compute this every time an
>operation is done, or if they just get this from memory (ie, is the parity
>bit valid after EVERY operation, or just loads from memory...?)

The parity flag indicates the parity of the low 8 bits of the result
of the last arithmetic or logical operation - it has nothing to do with
memory parity and since move instructions do not affect the contents of the
flags register a load from or a store to memory will not change the flag.
However most arithmetic and logical instruction on the X86 will cause it
to be updated - the only exceptions seem to be AAA, AAS, MUL, IMUL and the
bit scan and bit test and set/clear/complement instructions after any of
which the parity flag is undefined.
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Message-ID: <1993Jan12.195805.19499@sco.com>
Path: arc1-ca.pugleaf.net!sparky!uunet!hobbes!md
References: <C0r3oq.4Hu@cs.mcgill.ca>

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Newsgroups: comp.sys.intel
Path: arc1-ca.pugleaf.net!sparky!uunet!hobbes!md
From: md@sco.COM (Michael Davidson)
Subject: Re: Parity on iAPX x86 chips
Organization: The Santa Cruz Operation, Inc.
Date: Tue, 12 Jan 1993 19:58:05 GMT
Message-ID: <1993Jan12.195805.19499@sco.com>
References: <C0r3oq.4Hu@cs.mcgill.ca>
Sender: news@sco.com (News admin)
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