🚀 go-pugleaf

>  But the Intel handouts show a RISC processor in there, and imply large
>gains in performance if you "simply recompile for maximum performance."

If the P5 is a superscalar chip, but with *ABSOLUTELY NO CHANGES TO THE
INSTRUCTION SET* from the 80486, it can *STILL* be the case that you
have to recompile for maximum performance, because you might have two
sequence of instructions that run about equally well on the 486, but
don't run equally well on the P5, because the P5 might be able to launch
two instructions more frequently with one sequence than with the other.

I.e., there's no reason to conclude that there's some whizzo new RISC
instruction set just because they're suggesting recompiling for maximum
performance.

Furthermore, I wouldn't even conclude that there's some whizzo new RISC
instruction set given the block diagrams I've seen.  It could be that
the internal architecture of the chip involves an execution engine
similar to that of a RISC processor, and something that turns
386-family instructions into stuff that gets fed to that execution
engine, but that you can't just feed that execution engine some "native"
code from memory.

Yes, several people have claimed that there really is some native "RISC
mode" in the P5.  I'm not gonna believe *any* of you guys unless:

	1) you show me a document from Intel describing that native
	   mode;

	2) the chip is announced and Intel says it has such a mode.