🚀 go-pugleaf

In article <10308@inews.intel.com> dpeterso@mipos2.intel.com (David Peterson) writes:

>In article <1992Mar31.033110.28110@bilver.uucp> wbeebe@bilver.uucp (Bill Beebe) writes:
>>In article <1992Mar26.124338.24482@email.tuwien.ac.at> volker@vlsivie.tuwien.ac.at (Volker Hamann) writes:
>>
>>>Wharton in "BYTE Nov. 1989", the 486 uses 1-micron high-speed CMOS technology
>>                                           ^^^^^^^^
>>I thought the 486 is currently being built with .8 micron die size. At least
>>                                                ^^^^^^^^^
>>William H. Beebe, Jr. - wbeebe@bilver.UUCP

>  Here's what I know of the subject, which is not much :-). Intel is always
>trying to shink mature (and not so mature) products. The reason for this is
>that a smaller die size improves yeild. I don't know what the present process
>is for 486's, but since this device has been around for a couple of years 
>I'm sure that it's been shrunk at least once.

As I recall, the original 486-25's were built using 1 micron technology, but 
that from the 486-33 were redesigned to use the new .8 micron manufaturing 
process.

Andries
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