Article View: comp.sys.intel
Article #243Re: 486 transistor count, linesize
From: David Peterson
Date: Fri, 10 Apr 1992 15:34
Date: Fri, 10 Apr 1992 15:34
19 lines
1591 bytes
1591 bytes
In article <1992Mar31.033110.28110@bilver.uucp> wbeebe@bilver.uucp (Bill Beebe) writes: >In article <1992Mar26.124338.24482@email.tuwien.ac.at> volker@vlsivie.tuwien.ac.at (Volker Hamann) writes: > >>Wharton in "BYTE Nov. 1989", the 486 uses 1-micron high-speed CMOS technology > ^^^^^^^^ >I thought the 486 is currently being built with .8 micron die size. At least > ^^^^^^^^^ >William H. Beebe, Jr. - wbeebe@bilver.UUCP Here's what I know of the subject, which is not much :-). Intel is always trying to shink mature (and not so mature) products. The reason for this is that a smaller die size improves yeild. I don't know what the present process is for 486's, but since this device has been around for a couple of years I'm sure that it's been shrunk at least once. ----------------------------------------------------------------------------- David Peterson Intel Corp., M/S SC4-69, 2625 Walsh Ave. Santa Clara, Ca. 95052-9940 dpeterso@mipos3.intel.com
Technical Details
Message-ID:
<10308@inews.intel.com>Path:
arc1-ca.pugleaf.net!sparky!uunet!iWarp.intel.com|inews!mipos2!dpetersoReferences:
<1992Mar25.65145.13249@ms.uky.edu> <1992Mar26.124338.24482@email.tuwien.ac.at> <1992Mar31.033110.28110@bilver.uucp>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!iWarp.intel.com|inews!mipos2!dpeterso From: dpeterso@mipos2.intel.com (David Peterson) Newsgroups: comp.sys.intel Subject: Re: 486 transistor count, linesize Message-ID: <10308@inews.intel.com> Date: 10 Apr 92 15:34:33 GMT References: <1992Mar25.65145.13249@ms.uky.edu> <1992Mar26.124338.24482@email.tuwien.ac.at> <1992Mar31.033110.28110@bilver.uucp> Sender: news@inews.intel.com Reply-To: dpeterso@mipos2.UUCP (David Peterson) Organization: Intel Corporation, Santa Clara, CA Lines: 19