🚀 go-pugleaf

In article <1992Aug28.182116.4396@megatek.com> megatek!rstewart@uunet.uu.net writes:
> [ discussion about why the i860 failed deleted ]
>
>My guess is that it is not a superscalar design. The chip relies heavily
>of the code generating all the pipe lining. This makes  compiler
>writing difficult (right Larry?). It makes assembly coding difficult.

Right.

>It leads to slower nominal performance rates. While an i860 is very fast
>on an infinitely long vector:vector operation (100 mflop @ 50 M) for 
>floating point that doesn't vectorize, it is less than blazing. 
>
>Superscalar designs also handle concurrent execution of different processing
>units alot nicer. 
>
>So, if INTEL took an i960 core, expanded it to 64 bits wide, mix in floating
>point, of i860 speeds, with out that damned pipelining by hand stuff, 
>had some SHARED registers between the floating point
>and integer sections, did speculative instruction execution on the alu and
>fpu, provided a 64 bit alu which ops could be segmented into 
>2*32, 4*16, or 8*8 bit concurrent 2's compliment operations, AND ALLOWED THE
>ENTIRE DATA CACHE TO BE BOOT TIME SELECTABLE AS EITHER DATA CACHE OR MEMORY
>MAPPED FAST DATA STORAGE, I'd be happy, and I think it would sell, IMHO. 
>
>-Rich
>
>rstewart@megatek.com

All this stuff sounds like nice for imbedded systems, but much of it sounds
pretty useless for general purpose CPUs, at least the part about the segmenting
and the cache mapping.

I don't think that the hand pipelining is so bad, although being able to
issue multiple fp instructions without freezing would be fine.  However, I
do agree that the lack of superscalar between the integer, multiplier, and
adder is a problem.  If it were truly superscalar rather than dual-op+dual-mode,
it would be a lot easier to compile to.

I still think that good system designs can make the i860 competitive with
existing general-purpose risc chips.
-- 
Larry Meadows		The Portland Group
lfm@pgroup.com