🚀 go-pugleaf

In article <1992Aug28.182116.4396@megatek.com> megatek!rstewart@uunet.uu.net writes:
>
>>In article <TMH.92Aug26230950@doppel.first.gmd.de> tmh@doppel.first.gmd.de (Thomas Hoberg) writes:
>>>In article <BtLGIG.3q2@pgroup.com> I write:
>>>   Actually, the announcement was that Intel had admitted the failure of
>>>   the i860 as a general-purpose CPU.  They still intend to support it in
>>>   graphics and embedded applications; speculation is that they will also
>>>   support it for the iPSC MPP systems.  No followon has been announced,
>>>   but one would obviously be needed if they do indeed plan to continue to
>>>   use i860-like chips in the iPSC.
>>>
>>>Why did it fail, though? While there might be better CPUs today, I
>>>thought it pretty good when it came out. Was there anything seriously
>>>wrong with it (except that it'd do virtual caching)? Was it just that
>>>the various vendors were too busy promoting their own designs or
>>>tuning their old architectures? Is it just bad luck that nobody
>>>decided to pick it up or is there something about the i860 that I
>>>missed?
>>
>
>My guess is that it is not a superscalar design. The chip relies heavily
>of the code generating all the pipe lining. This makes  compiler
>writing difficult (right Larry?). It makes assembly coding difficult.
>It leads to slower nominal performance rates. While an i860 is very fast
>on an infinitely long vector:vector operation (100 mflop @ 50 M) for 
>floating point that doesn't vectorize, it is less than blazing. 
>
>Superscalar designs also handle concurrent execution of different processing
>units alot nicer. 
>
>So, if INTEL took an i960 core, expanded it to 64 bits wide, mix in floating
>point, of i860 speeds, with out that damned pipelining by hand stuff, 
>had some SHARED registers between the floating point
>and integer sections, did speculative instruction execution on the alu and
>fpu, provided a 64 bit alu which ops could be segmented into 
>2*32, 4*16, or 8*8 bit concurrent 2's compliment operations, AND ALLOWED THE
>ENTIRE DATA CACHE TO BE BOOT TIME SELECTABLE AS EITHER DATA CACHE OR MEMORY
>MAPPED FAST DATA STORAGE, I'd be happy, and I think it would sell, IMHO. 
>
>-Rich
>
>rstewart@megatek.com

Wait up.  You speak as if the i860 is not superscalar; it sure as heck IS!

It has MULTIPLE pipelines, which can be used concurrently.  That's the
textbook definition of superscalar microprocessing.

Mark Neidengard
mneideng@cosmos.acs.calpoly.edu