Article View: comp.sys.intel
Article #553Re: Future of i860 line
From: william E Davidsen
Date: Mon, 31 Aug 1992 17:37
Date: Mon, 31 Aug 1992 17:37
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In article <1860@junkyard.UUCP>, joe@junkyard.UUCP (Joseph Sarkes) writes:
| Perhaps what intel will do is jam the 860 onto the 586 or 686 die
| as an accellerator/vector fp unit and share the caches tween the
| two and give more people(the entire 86 market place) the chance to
| see how neat a chip it is.
The P5 chip that Intel was going to release had a faster FPU, although
I don't know if it was related to the 860 FPU or not. From remarks made
at FORUM I now believe that the P5 as it has been reported will never be
available to the public. The Intel speaker talked around the topic, but
implied that the chip was simply not manufacturable in commercial
quantities and that Intel is going to a new process to get the chip size
down, speed up, power consumption down, and yield up.
Note that I am getting this from two people who were at the talk, I
missed it myself. If any other readers were there please add to this.
--
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
I admit that when I was in school I wrote COBOL. But I didn't compile.
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Path: arc1-ca.pugleaf.net!sparky!uunet!crdgw1!rdsunx.crd.ge.com!ariel!davidsen From: davidsen@ariel.crd.GE.COM (william E Davidsen) Newsgroups: comp.sys.intel Subject: Re: Future of i860 line Message-ID: <1992Aug31.173722.8046@crd.ge.com> Date: 31 Aug 92 17:37:22 GMT References: <Btr4Iz.GB9@pgroup.com> <1860@junkyard.UUCP> Sender: usenet@crd.ge.com (Required for NNTP) Reply-To: davidsen@crd.ge.com (bill davidsen) Organization: GE Corporate R&D Center, Schenectady NY Lines: 19 Nntp-Posting-Host: ariel.crd.ge.com