Article View: comp.sys.intel
Article #558Re: Intel 486 on-chip cache in a multiprocessor config ?
From: Raul Izahi Lopez Hernandez
Date: Tue, 01 Sep 1992 08:23
Date: Tue, 01 Sep 1992 08:23
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In article <1992Aug31.170710.7898@jpradley.jpr.com> adykes@jpradley.jpr.com (Al Dykes) writes:
>Can the 486 on-chip cache maintain cache coherency in
>a shared memory MP configuration ?
>
>Al Dykes
>---------
>adykes@jpr.com
Yes, it has bidirectional address lines.
I don't recall, however, if it can implement Exclusive/Shared/Dirty/Invalid
status on the cache and source its data to other caches, or will only flush
the cache or a single line when an address in its cache is given to the chip
from an outside system.
--
-----> All opinions expressed here are my own, not IBM's <-----
Raul Izahi Lopez Izahi Engineering
izahi@bsc.no IBM Bergen Environmental Sciences and Solutions Centre
Thormoehlensgate 55, 5008 Bergen, NORWAY (47-5)54-4653
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Newsgroups: comp.sys.intel Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!aun.uninett.no!alf.uib.no!newsroom.bsc.no!izahi From: izahi@bsc.no (Raul Izahi Lopez Hernandez) Subject: Re: Intel 486 on-chip cache in a multiprocessor config ? Message-ID: <1992Sep1.082358.14710@newsroom.bsc.no> Sender: usenet@newsroom.bsc.no (Usenet News Administrator) Organization: Bergen Scientific Centre, Bergen, NORWAY References: <1992Aug31.170710.7898@jpradley.jpr.com> Date: Tue, 1 Sep 1992 08:23:58 GMT Lines: 18