Re: Future of i860 line

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Article #559

#559

From: Larry Meadows
Date: Tue, 01 Sep 1992 15:15

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In article <1992Aug31.151640.16824@megatek.com> megatek!rstewart@uunet.uu.net writes:
>Stop this. You can bypass cache on lots of chips. Most caching cpu's
>can have cache bypassed in the page tables. A second way, if your board
>is designed to do it, is a software toggle of some sort. I think, most
>modern cpu's, have a cache enable/disable pin.
Yeah, but at full bus bandwidth in user mode in a way that works for every
system?
>
>And finally, you do not want to use pfld's that might access memory
>that is in a cachable address range. (Right Larry?).
Easy if you are vectorizing.
-- 
Larry Meadows		The Portland Group
lfm@pgroup.com

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Path: arc1-ca.pugleaf.net!sparky!uunet!pgroup!lfm

References: <1992Aug29.031847.28867@nas.nasa.gov> <Btr4Iz.GB9@pgroup.com> <1992Aug31.151640.16824@megatek.com>

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Newsgroups: comp.sys.intel
Path: arc1-ca.pugleaf.net!sparky!uunet!pgroup!lfm
From: lfm@pgroup.com (Larry Meadows)
Subject: Re: Future of i860 line
Message-ID: <Btwnp7.3MH@pgroup.com>
Date: Tue, 1 Sep 1992 15:15:07 GMT
References: <1992Aug29.031847.28867@nas.nasa.gov> <Btr4Iz.GB9@pgroup.com> <1992Aug31.151640.16824@megatek.com>
Organization: The Portland Group, Portland, OR
Lines: 14

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