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Article #719Re: Zero wait state and caches
From: Paul de Bra
Date: Mon, 08 Oct 1990 12:36
Date: Mon, 08 Oct 1990 12:36
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1708 bytes
In article <188@nat-3.UUCP> root@nat-3.UUCP (nat-3 System Administrator) writes: >Hello -- > > I have a 25 MHz 386 motherboard with no cache, but with >plenty of 70 ns DRAM that provides zero wait state performance. >Is there any reason that a cache would boost performance on my >machine? My (very limited, probably incorrect, software-oriented) >reasoning is NO: At 25 Mhz, 70ns DRAM will not provide zero wait state performance for 2 reasons: 1) 70ns is too slow. you probably have some kind of interleaved memory which starts fetching a memory word as soon as the previous one is requested. You have approx 35ns for zero wait state, so if you start the memory read ahead of time you can get zero wait state, otherwise you don't. As most programs switch back and forth between fetching instructions and data, you will not experience zero wait state behaviour. 2) The DRAM needs to be refreshed, which may occasionally cause extra wait states if you try to access the part of memory that is being refreshed. A cache system provides zero wait states on a cache hit, but one or two wait states on a cache miss. Given sufficient cache memory (64k or more) the hit rate is fairly close to 100%, and the performance increase is substantial. Paul. (debra@research.att.com)
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!mcsun!hp4nl!svin02!wsinpdb From: wsinpdb@svin02.info.win.tue.nl (Paul de Bra) Newsgroups: comp.sys.intel Subject: Re: Zero wait state and caches Keywords: wait states, cache Message-ID: <1466@svin02.info.win.tue.nl> Date: 8 Oct 90 12:36:39 GMT References: <188@nat-3.UUCP> Organization: Eindhoven University of Technology, The Netherlands Lines: 28