Article View: comp.sys.misc
Article #646Re: 74LS is too slow. Maybe?
From: Jerry Bemis
Date: Thu, 25 Apr 1991 16:44
Date: Thu, 25 Apr 1991 16:44
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In article <1067@eplunix.UUCP> raoul@eplunix.UUCP (Nico Garcia) writes: >In article <1991Apr23.013116.3769@nntp-server.caltech.edu>, josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) writes: >> My problem is that a couple of 74LS gates will already add up to about 40ns >> to the access time... Ergo, wait states - something that I don't want >> to have if I can get away without it. > >Hmmm. I don't know how the clever digital people did it, but what's >the net delay on a PAL down to these days? Also, can you cleverly >run your gates off the previous clock cycle or the latter half of >it? It's a bit of a kludge, but it might work.... > > >-- > Nico Garcia 5nS PALs are out these days. Call AMD at 800 222-9323
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!usc!apple!sun-barr!newstop!sun!amdcad!brahms!lpdjbReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!usc!apple!sun-barr!newstop!sun!amdcad!brahms!lpdjb From: lpdjb@brahms.amd.com (Jerry Bemis) Newsgroups: comp.sys.misc,sci.engr,sci.electronics Subject: Re: 74LS is too slow. Maybe? Keywords: 74LS TTL Logic Computer Design Timing Message-ID: <1991Apr25.164408.16614@amd.com> Date: 25 Apr 91 16:44:08 GMT References: <1991Apr23.013116.3769@nntp-server.caltech.edu> <1067@eplunix.UUCP> Sender: usenet@amd.com (NNTP Posting) Organization: Micro ; Sunnyvale, CA Lines: 15