🚀 go-pugleaf

[In the message entitled "Gatewayed mail message" on May  4, 12:44, bob von borstel writes:]
>   I have another ? that you can answer.  When talking to my NS distributor,
> he found 2 versions of the 32381 fpu, a u and a v version.  I assume I want
> the u version, but can you tell me what the difference is?
The U version is in a ceramic package, and is a PGA (Pin Grid Array).
The V version is in a plastic package, and is a PLCC.

You _should_ be able to use the V version. It is significantly less
expensive. We have ordered a couple to try from the local NS field office
here, but they have been quite slow in getting them to us. I suspect that
they may not be in full production yet. As soon as we get one working,
we will let you know.

BTW - steve.ligett@mac.dartmouth.edu is putting together parts kits
for those that want them. By purchasing in volume, the prices will be
better than you can get on your own - this includes the CPU/FPU/ICU.


>   When I purchase the 532/381 parts, since they are $$$, and the cost
> differential between 25mhz and 30mhz isn't too extreme, is it possible
> to buy the 30mhz parts, and drive the board at 25mhz, and then 'maybe'
> later down the road, replace the 50mhz crystal with 60mhz, or are your
> design tolerances strictly 25mhz?

You are welcome to try this. The design is for 25 Mhz, and every nanosecond
counts. Really. 25 Mhz is a realistic operating frequency, and is picked for
the optimal balance between memory wait states and system performance.
Going to 30 Mhz would really require another wait state on the memory -
reducing memory bandwidth by 33% (3 clocks instead of 2). Right now,
we get 50 megabytes per second at 25 Mhz - at 30, it would be 40 meg/sec.
While the caches on the 532 help, a 10 meg/sec loss in memory bandwidth
would hurt! (The 32016 has a 4 meg/sec bandwidth, the 32032 an 8 meg/sec).

If you do try to push to 30 Mhz without re-doing the memory timing, you
will need to carefully evaluate the worst case paths, and increase the
speed of the PALs and memory devices to match. George has posted on this
topic in the past, let me see... <rummage, rummage, shuffle> Ah HA! 

<From pcdig13>

In-Reply-To: Dave Mason's message on Dec 12, 15:45.
X-Mailer: Mail User's Shell (6.2 5/11/88)
To: pc532@daver.UU.NET
Subject: Re: FPU
Message-Id: <8912122348.AA23965@wombat.UUCP>
Date: 12 Dec 89 23:48:24 PST (Tue)
From: george@wombat.UUCP (George Scolaro)
Status: OR

> Could the board be run at 30MHz with faster DRAMs?  I just looked and
> 70ns rams are about 30% more expensive than 80ns.  George's BOM says
> 85ns rams, so if you boosted the clock to 30MHz 70ns rams should
> work.... ???  Would there be any advantages (or would it even be
> possible) to run the processor at 30MHz with wait states for the
> memory?

No, I'm afraid not. The design is very balanced to 25mhz, achieving
the 0 wait state read/write on first access & 1 wait state in burst is
very tight. The worst case margin is a couple of nanoseconds in the
critical paths. Pushing to 30mhz would increase the number of wait states,
definitely 1 on read/write and probably 2 during the burst. The performance
gained by running at 30mhz would be mostly lost via the wait states. The
10 mips sustained at 30mhz is for zero wait states, and experimenting has
shown that each wait state costs you 7% or more. Dhrystone can show up
to a 20% hit per wait state.

Besides, the cost of the 32532+381 would definitely be a lot higher at
30mhz, since you would then be paying for 'el primo parts. Note we are
still hoping that NS will do a good deal with us, and this would probably
be the case on the volume parts not their top of the line stuff.

Dhrystone 2.1 gets 10869 on this board, note this isn't version 1.1 which
	[note: current pc532 is 11111 due to optimized pals <dlr>]
gave much higher values (due to cheating optimizing compilers). Our 25mhz
compaq 386's (with 64k cache) get around 6-7000 dhrystones. Note: Dhrystone
is very very memory bandwidth sensitive, this is where wait states really
hurt performance a lot.

Note some more numbers to place the pc532 with regard to other systems:

Cray 2 gets	9375 - 13043 (new compiler)
Aeon (532)	9998
Encore (532)	11117 - 11223
Sun 4/280	10889
Vax 8700	10791 - 11082
Amdahl 5990-700 gets 91463/cpu


> 15 MIPS peak/ 10 MIPS sustained makes a good thing (pc532) sound even
> better.... but maybe I'm just getting greedy.  Actually, I just want

Yes you definitely are, but then we all are. We jiggled the design for a
long time (I started designing the pc532 last year around April and had a
wirewrap prototype running around June or so of '88), so the choice of 25mhz
is based on a lot of design tradeoffs. Besides, you wouldn't really notice a
20% (less the wait state loss) performance difference, it would be like
comparing an 8mhz 286 to a 10mhz 286. If you want to try and push to 30mhz,
you can change the pal equations, get faster memory, get faster NS parts and
use 7.5 ns PALs and it might all work (I'll leave this as an exercise for the
interested reader...), but I'm happy to let it sit at 25mhz, the parts are a
lot cheaper!

> BTW, I don't think I've said it yet, but definitely count me in for 2
> boards (plus associated PALs/PLAs and EPROMs).  Early February
> delivery time is fine. 

Fine, you're on the list.

Note: 1 nanosecond is a short piece of wire.

best regards,

-- 
George Scolaro
george@wombat
(try {pyramid|sun|vsi1|killer} !daver!wombat!george) [37 20 51 N / 122 03 07 W]


-- 
Dave Rand
{pyramid|hoptoad|sun|vsi1}!daver!dlr	Internet: dlr@daver.bungi.com