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Article #2688Re: Sparc5 vs. Sparc10
From: James Lockwood
Date: Fri, 18 Feb 2000 00:00
Date: Fri, 18 Feb 2000 00:00
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2975 bytes
Craig Dewick (cd@lios.apana.org.au) wrote: : Sparc 10's use Mbus CPU modules, and there are two MBus slots on the board. : Depending on the bootROM, you can use anything from a single lowly 40 MHz : SM-41 (Supersparc) module right up to a pair of 150 MHz SM-151 (Hypersparc) : modules. Or even a lowly 33MHz SM20 with no e-cache at all. : Not sure what you mean by 'interwork'... They do have to be inserted in a : specific order in Sparc 10's though. There must be a SIMM inserted into the first slot. The others can be arranged in any order though there are minor benefits in physical memory mapping and cooling gained by following certain arrangements. : It depends on the CPU(s) fitted to the 10. The 170 MHz Sparc 5 has a single, : 170 Mhz Microsparc-2 processor. The Microsparc CPU family was the : predecessor to the SuperSparc (up to SM-61), Supersparc-2 (SM-71 and SM-81) : and Hypersparc processor(s) most commonly used in Sparc 10's, 20, 4/6x0's, : etc. Actually, microSparc (as used in the Classic/LX) and microSparc-II (used in the Sparc 4/5) were developed concurrently with SuperSparc. SuperSparc was released first (in 1992), microSparc-II didn't even arrive until 1994. The two processors are very different architecturally, SuperSparc accomplishes more work per clock cycle but was harder to scale up in clock speed. The SM20 and SM30 existed solely because TI was having trouble manufacturing 40MHz SuperSparcs in quantity. : Sparc 5's can't have any more CPU's added, and there are no upgrades : available beyond the 170 Mhz model. So in terms of scalability, etc. the : Sparc 10 wins over the Sparc 5, but of course the 170 Mhz CPU in your Sparc : 5 is going to beat most combinations of low-end SuperSparc CPU modules in a : Sparc 10. Both machines are going to give different benchmarks for different : applications, so doing comparisons isn't as simple as it first looks. Absolutely. Even comparing a single CPU SS10 vs a SS5 is tough, as the SS10 is designed around a large cache and high cache miss cost while the SS5 is designed around a small cache and low cache miss cost. -James
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: f4671,c651c7cb20d2e6d X-Google-Attributes: gidf4671,public X-Google-Thread: 10d053,ec8c818fd0676b73 X-Google-Attributes: gid10d053,public From: james@foonly.com (James Lockwood) Subject: Re: Sparc5 vs. Sparc10 Date: 2000/02/18 Message-ID: <9m0r4.8452$Ev4.189900@nnrp1-w.snfc21.pbi.net> X-Deja-AN: 587154014 References: <slrn8amr2j.1q3.amour@kolombangara.flash.net> <88i1au$6jc$1@jedi.apana.org.au> Followup-To: comp.sys.sun.hardware,aus.computers.sun X-Complaints-To: abuse@pacbell.net X-Trace: nnrp1-w.snfc21.pbi.net 950833669 207.215.187.27 (Thu, 17 Feb 2000 16:27:49 PST) Organization: The Electric Mayhem X-Foonly: 36 bits forever! NNTP-Posting-Date: Thu, 17 Feb 2000 16:27:49 PST Newsgroups: comp.sys.sun.hardware,aus.computers.sun