🚀 go-pugleaf

In article <2r6bsnINNagr@life.ai.mit.edu> mikc@gnu.ai.mit.edu (Mike Coughlin) writes:
>In article <2qpn1p$6tv@kralizec.zeta.org.au>,
>Craig Dewick <craig@kralizec.zeta.org.au> wrote:
>>I've seen reference to a version of the 8530 that has a FIFO buffer
>>built into the chip which acts transparently as though it's not
>>there when used with software designed to work with the standard
>>chip. Is this true? If so, who makes it and where could I get a
>>couple?
...
>The new versions that have FIFO's are numbered 85130 and 85230 and
>are also made by Zilog.

The 8530 "SCC" HAS an rx fifo, but it's only 3 characters deep.  The
85230 "ESCC" (which my databooks says was introduced in 1981, so it's
hardly recent) extends this to 8, and has a 4-byte tx FIFO as well.
The ESCC also does some cleanup and extensions, but nothing that's
usually noticed by async applications.

The problem with dropping the ESCC into an existing system is that SCC
drivers usually try to drain the data/error fifos on startup and/or
error recovery by doing 3 sucessive reads and discarding the data.  A
trivial fix, IF you have sources!  But if you had sources, you could
drain the FIFO on an rx interrupt, rather than taking 3 interrupts to
do it!!  If the deeper FIFO's need to be enabled (I don't recall) you
will need to do the enable to get the benefit.  I suspect all this
would be easy to do in NetBSD (providing the sun3 port is available).

Phil Budne
Consultant