🚀 go-pugleaf

andrew@isdg.cs.hull.ac.uk (Andrew Stewart) wrote:
> Does anyone have experience of using the MEMWAIT pin on a T8 or a T4 to
> stretch the memory cycle? I have a circuit that doesn't appear to work,
> despite following the timings laid down in the T800 product description.

I'm not an expert, but when working in the company of experts, there was
quite an explosion when we found out we'd have to change the hardware to
work around metastability problems MemWait has if it is changed too close
to a clock edge.  I never did learn the exact details, but I am sure of
those few facts.  Beat on Inmos for details.

> As far as I can see, the memory cycle is ending *despite* MEMWAIT being held
> low; I'm taking memwait low at the same point in the cycle as MS3 goes low,
> and I'm using the internal memory configuration available on AD7. (The
> slowest multiplexed DRAM time).

Try some sort of delay to slow down the assertion of Wait a bit.  S3 comes
on a clock edge, and MemWait doesn't take to being fed that.

> On the logic analyser, I get this (amid lots of other rubbish):
> 
>               <-    ~200ns    ->
> 
> MS0:    ------|________________|-------------
> MS2:    -----------|___________|-------------
> MS3:    -------------|_________|-------------
> MEMWAIT:-------------|_________|-------------
> 
> which looks quite odd.

Very odd.  Could you perhaps include ProcClockOut for reference?
That memory configuration is diagrammed in the data book, and what
puzzles me is that S0 and S2 are so far apart, while S2 and S3 are
so close.  They should be 25 and 50 nanoseconds apart, respectively.
And shouldn't be affected by the MemWait pin, since nothing's happened
to it yet.  Or is this access cycle right after another that also used
the MemWait pin?  If so, are the patterns highly repeatable?
Metastability would be evidenced by erratic patterns.
-- 
	-Colin (uunet!microsoft!w-colinp)