Good Memory

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2 total messages Started by Patrick Van Renterghem / Transpu... Tue, 28 Feb 1989 08:45

#2509

Author: Patrick Van Renterghem / Transpu...
Date: Tue, 28 Feb 1989 08:45

21 lines
1748 bytes

Hi,
 
Long time ago, there was a discussion here about lowering the clock frequency
(to 500 kHz e.g.) for minimizing the power consumption. Who remembers anything
of that ? More precisely, I would like to know if it is possible (I think it is,
playing around with DisablePLL and your own ClockIn) and if someone has tried
it. With T800's of course.
 
Thanks in advance,
 
*****************************************************************************
* Patrick Van Renterghem,     BITNET: pvr@bgerug51.bitnet                   *
* R&D Assistant,              EDU:    pvr%bgerug51.bitnet@cunyvm.cuny.edu   *
* State University of Ghent   UUCP:   mcvax!bgerug51.bitnet!pvr             *
* Belgium                     JANET:  PVR%earn.bgerug51@earn-relay          *
*                                                                           *
* Automatic Control Lab/The Transputer Lab,   Tel: +32 91 22 57 55 ext. 313 *
* State University of Ghent,                  Fax: +32 91 22 85 91          *
* Grotesteenweg Noord 2,                                                    *
* B-9710 Ghent-Zwijnaarde, Belgium                                          *
*****************************************************************************

Re: Good Memory

#2533

Author: Andy Hamilton
Date: Wed, 08 Mar 1989 00:18

43 lines
2266 bytes

In article <8902281135.AA05126@uk.ac.ox.prg>
PVR%bgerug51.earn@NSS.CS.UCL.AC.UK (Patrick Van Renterghem / Transputer
Lab) writes:

>Long time ago, there was a discussion here about lowering the clock frequency
>(to 500 kHz e.g.) for minimizing the power consumption. Who remembers anything
>of that ? More precisely, I would like to know if it is possible (I think it is,
>playing around with DisablePLL and your own ClockIn) and if someone has tried
>it. With T800's of course.

Yes, this has been done.  Smith Associates (address below) developed a
fault-tolerant demonstrator system for SPACE applications (European
Space Research and Technology Centre (ESTEC) contract
6946/86/NL/PP(SC)).  The demonstrator ran some image compression stuff
and mission-critical satellite orientation control.  As a result of this
demonstrator, ESTEC is now developing a system to be launched on a
future University satellite (perhaps UOSAT3).  In this design, the clock
speeds of the transputers are reduced to conserve power (less than
half-a-wot per transputer module), and the system keeps going. 
Brilliant.

	For further information on this, you could contact

		Richard Armstrong,
		Smith Associates Ltd,
		Surrey Research Park,
		Guildford,
		Surrey GU2 5YP,
		ENGLAND.

		Tel (0483) 505565.

	Unfortunately, I don't have an email-id for this.

	Hope this is useful.

	Cheers,
		Andy Hamilton.

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