🚀 go-pugleaf

           DEPARTMENT OF COMPUTER SCIENCE
             COLORADO STATE UNIVERSITY

		    BARNEY'S
           MONDAY AFTERNOON CLUB SEMINAR

	Speaker:	Doug Hunt
	                Hewlett-Packard Company
	                Engineering Systems Lab

	   Date:	November 18, 1996
	   Time:	3:30 - 4:30 p.m.
	  Place:	100 USC

	  Refreshments:  following the talk

	   Host:	Walid Najjar
		        1-7026
	                najjar@cs.colostate.edu

        ADVANCED PERFORMANCE FEATURES OF THE
                  64-BIT PA-8000

    The PA-8000 is Hewlett-Packard's first CPU to 
  implement the new 64-bit PA2.0 architecture.  It 
  combines a high clock frequency with a number of 
  advanced microarchitectural features to deliver 
  industry-leading performance on commercial and 
  technical applications while maintaining full 
  compatibility with all previous PA-RISC binaries.  
  Among these advanced features are a fifty-six 
  entry instruction reorder buffer to support out-
  of-order execution, a branch target address cache, 
  branch history table, support for multiple out-
  standing cache misses and dual integer, load/store, 
  floating point multiply/accumulate, and divide/
  square root units which allow execution of four 
  instructions per cycle.  Together, these features 
  enable the PA-8000 to sustain superscalar opera-
  tion on a wide variety of workloads.

  Keywords:  superscalar, out-of-order, micro-
  processor, CPU, PA-RISC