🚀 go-pugleaf

> I think Miya's point, in complaining that we were talking about
> the Cray size in bytes when it is really in words, is that when
> you're talking about address decoding, 256MW is NOT the same
> problem as 2GB.  It's three bits less.

THAT depends on how your memory subsystem works.  One can imagine a memory
system that works in 32-bit or 64-bit words; the memory address would be the
address of a 32-bit or 64-bit memory word, and the low-order 2 or 3 bits
would be used by the CPU to pick off the byte from that word.

In fact, somebody *did* imagine such a memory subsystem; a company called
Digital Equipment Corporation came out with a machine in the Virtual Address
eXtension line of machines which had a Synchronous Backplane Interconnect to
which memory was attached; addresses were 28-bit addresses of 32-bit
longwords.

Actually, in this case the memory controller may have handled byte selection
and stuffing; the SBI has "read masked" and "write masked" commands that
used a 4-bit mask to indicate which bytes appeared on the data lines during
the operation.  However, this stuff may have been there mostly for the
benefit of the UBA, where the bytes selected would actually affect the sorts
of UNIBUS operations performed; the memory controller could always fetch a
32-bit longword and just use some NAND gates or something on the "read
masked" and use read-modify-write cycles and 2-1 multiplexors on the "write
masked" operations; it doesn't have to select one of four bytes, just one of
two.

If the VAX hadn't descended from a line of machines with a byte-addressible
bus, it might have been possible not to bother giving the "which bytes are
of interest" information to nexi on the SBI at all, and do *all* of the byte
handling in the CPU.  
-- 
	Guy Harris
	{ihnp4, decvax, seismo, decwrl, ...}!sun!guy
	guy@sun.com (or guy@sun.arpa)