Article View: net.micro.16k
Article #180Re: Questions about Scaled Index addressing mode
From: Andy Fyfe
Date: Sun, 10 Mar 1985 02:48
Date: Sun, 10 Mar 1985 02:48
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1518 bytes
The following is taken from "NS16000 Instruction Set Reference Manual",
dated August, 1983 (and (c) National Semiconductor).
From the section on access classes, table 4-1
----------------+----------------------------------------------
| Access Class
Addressing +----------------------------------------------
Mode | read write rmw addr regaddr
----------------+----------------------------------------------
Register | Rn,Fn Rn,Fn Rn,Fn (Rn) Rn,Fn
Immediate | legal ----- ----- ----- -----
Top Of Stack | Push Pop (SP) (SP) (SP)
----------------+----------------------------------------------
Note (2): Using Scaled Indexing in an addressing mode overrides
the access class and forces it to addr.
Thus, for example, R0[R1:B] means (R0)[R1:B].
Hope this answers your question.
--Andy Fyfe ...!{decvax, allegra, ihnp4, et. al}!watmath!wjafyfe
wjafyfe@waterloo.csnet
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site watmath.UUCP Path: arc1-ca.pugleaf.net!utzoo!watmath!wjafyfe From: wjafyfe@watmath.UUCP (Andy Fyfe) Newsgroups: net.micro.16k Subject: Re: Questions about Scaled Index addressing mode Message-ID: <11866@watmath.UUCP> Date: Sat, 9-Mar-85 21:48:12 EST Article-I.D.: watmath.11866 Posted: Sat Mar 9 21:48:12 1985 Date-Received: Sun, 10-Mar-85 07:44:18 EST References: <200@gitpyr.UUCP> <1821@sdcrdcf.UUCP> Reply-To: wjafyfe@watmath.UUCP (Andy Fyfe) Distribution: net Organization: U of Waterloo, Ontario Lines: 24