🚀 go-pugleaf

In article <200@gitpyr.UUCP> dcs@gitpyr.UUCP (David Sowell) writes:
>------
>
>I have some questions about the NS32032's addressing modes:
>
>	What does the Scaled Index addressing option do when applied
>	to a Register addressing mode?  In other words, what does
>	something like "MOVW R1[R3:B],R0" do?  
>
>	What results from doing something like "ADDR R1,R0"?
>

In both of these examples the "access class" for the register operand
is "addr" (scaled index addressing mode overrides the access class and
forces it to "addr").

Since taking the address of a register doesn't make much sense (unless
you're a PDP-10 I guess), National defined this case to be equivalent
to 0(Rn).  In other words, MOVW R1[R3:B],R0 puts the contents of the
word at location (R1+R3) into the low word of R0 (upper word of R0 is
unchanged) and the instruction ADDR R1,R0 is equivalent to MOVD R1,R0.

This stuff also happens for Top of Stack addressing mode.  In access
class "addr", it means 0(SP).

This "strange behaviour" is a minor win for code density cause normally
0(Rn) costs at least 1 byte for the displacement (displacements are
either 1, 2 or 4 bytes).

	Steve Glaser
	tektronix!steveg