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Article #1466Re: 68000 Memory Managment
From: Erik Freed
Date: Fri, 29 Aug 1986 05:11
Date: Fri, 29 Aug 1986 05:11
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1356 bytes
> The delay from RAS to CAS required/accepted by most DRAMS is about the same
> is running the address lines thru a mapping ram or adder/comparator based mmu.
> Addresses and function codes precede AS by half a clock giving a little more
> head room. RAS can be started without knowing if the translation will be
> valid, since witholding CAS is a refresh cycle.
>
The basic arguments seem real sound as presented by this gentlemen and
I myself wondered why it would be so difficult to add memory management.
I wish that he had worked on the ST!!.
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Erik James Freed
Aurora Systems
San Francisco, CA
ptsfa!aum!freed
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!lll-crg!nike!ucbcad!ucbvax!hplabs!qantel!ptsfa!aum!freed From: freed@aum.UUCP (Erik Freed) Newsgroups: net.micro.atari16,net.micro.amiga,net.micro.68k Subject: Re: 68000 Memory Managment Message-ID: <744@aum.UUCP> Date: Fri, 29-Aug-86 01:11:01 EDT Article-I.D.: aum.744 Posted: Fri Aug 29 01:11:01 1986 Date-Received: Sat, 30-Aug-86 10:08:58 EDT References: <508@elmgate.UUCP> <64@mit-prep.ARPA> <510@elmgate.UUCP> <417@atari.UUcp> <271@dmsd.UUCP> Organization: The Aurora Systems Bunch Lines: 17