🚀 go-pugleaf

In article <937@cit-vax.Caltech.Edu> wen-king@cit-vlsi.UUCP (Wen-King Su) writes:
><<->>
>
>This is only a note on John Bass's article about a way to do virtual
>memory with little or no extra cost in time.  There is a catch to
>hiding MMU operations between RAS and CAS, though I do not know whether
>this applies to the ST.  The high speed CAS only block transfer
>operation available in many DRAMs is rendered useless since contiguous
>column addresses in a DRAM chip are no longer contiguous in 68K's
>address space.  I am not familiar with the graphic hardware of the ST,
>but the block transfer modes of the DRAM chips are well suited for high
>speed sequential access of blocks of memory that is typical to bitmap
>graphic systems.

This isn't really too much of a problem, since implementing page mode
operations for the processor is really not much fun without some clues
from the cpu (see Fairchild Clipper and Z80,000).  The big loss is with
graphics, especially with video DRAM, since you loose the linear relation
between addresses and shift-register or page mode accesses.

Of course one can argue that the display memory need not be relocated,
perhaps just protected via a storage key of some sort, but then your
system is starting to get complicated...

-- 
George Robbins - now working with,	uucp: {ihnp4|seismo|caip}!cbmvax!grr
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