🚀 go-pugleaf

On Wed, 21 Apr 2004 17:48:15 +0200, "5hinka" <anonim99@poczta.wp.pl>
wrote:

>How to build a phase detector??
>I know that normal design is two flip-fops and NAND gate but it works only
>with phase difference between signals smaler than 1 (T).  How could I
>possibly build a phase detector when phase difference between signals is up
>to 10-20 (T)??  It could be hole digital or digital/analog solution.
>Anybody know any suitable links??
>Greetings
>5hinka

The huge jitter only occurs at low frequencies.

Firstly, let's fix the terminology.  Your 'T' is more commonly
referred to as a Unit Interval (UI) when measuring jitter on a 2Mbit/s
circuit.

According to ITU-T G.823 (and a few others), the maximum tolerable
jitter on an E1 is 1.5UIp-p in the band 20Hz - 2400Hz, and 0.2UIp-p in
the band 18kHz - 100kHz.  Other specs indicate that the jitter /
wander may be as high as 18us p-p (36.8UIp-p) in the band from (1/1
day) to 0.8138Hz.  (If you draw this on a graph, there's a nice
-20dB/decade slope between the segments.)

Since you are making test equipment, you should be able to generate
and measure jitter with a higher amplitude than this, say by at least
6dB.  Your 10-20 UI figure sounds reasonable, but only at mid
frequencies.

I suggest that a more reasonable specification for test equipment
would be:
 > 80   UIp-p, for frequencies up to 0.81Hz
 >  3   UIp-p, for frequencies between 20Hz and 18kHz
 >  0.4 UIp-p, for frequencies greater than 18kHz.

I assume you are tracking the incoming phase with a PLL.  If the PLL
has a loop bandwidth of > 1.5 * 18kHz, the phase detector inside the
PLL will never see a phase difference of more than 2 UI p-p, which
means that a standard phase detector can be used without going outside
its linear range.

Regards,
Allan.