🚀 go-pugleaf

Richard wrote:
> Al Borowski wrote:
> 
>>Just 2 quick questions. I'm hooking a 32kb X 8 chunk of SRAM up to a
>>pic. PIC I/O pins are running short, so is it OK to connect pin X
>>directly to the output enable Pin on the SRAM, and connect a NOT gate
>>from output enable to write enable? If so, I can us pin X as a read /
>>write pin on the SRAM.
> 
> 
> New turf for me too, but I've been studying Samsung's SRAM with similar
> questions.  I don't know if Samsung's SRAM works uniquely, but here's
> what I'm gathering:
> 
> Per their data sheet, /OE is Don't Care (or overridden by /CS) for all
> operations except /WE.  So it would seem that /OE could be hardwired,
> leaving /CS to control whether the chip is selected and /WE to toggle
> the read/write behavior.  Timing would be:
> 
> To read:
> * Set the address on the bus
> * Clear /WE and enable /CS
> * Read byte
> * Clear /CS
> 
> To write:
> * Set the address and data on the bus
> * Enable /WE and /CS
> * Clear /WE and /CS
> 
> If /CS and /WE pins are on the same port, it would seem possible to set
> them in one operation, followed by the next step without a wait cycle,
> depending on the CPU clock.
> 
> As I said, something I'm only just exploring myself, so commentary is
> welcome...
> 
> http://www.samsungusa.com/download/semiconductors/sram/k6t0808c1d.pdf

You may want to check out the http://www.ramtron.com/ product line. 
They offer I2C and SPI serial FRAM chips, which allow 1E10 or more 
read/write cycles, are fast and non-volatile as well.  They interface 
very nicely to a PIC or other micro.

- Troy