🚀 go-pugleaf

>From: Ernie Oporto <EAO102@psuvm.psu.edu>
>Subj: Help with refresh/record scheme needed!
>Date: Tue, 17 Nov 1992 00:22:18 EST
>
>Well, now that I got the pin-outs for those 41256 DRAM chips, I'm going
>to need help figuring out how to do the refresh cycles.  I'm stumped on
>this one, folks.  I'm continuously recording voice/sound for 8 seconds,
>yet the DRAMs need to be refreshed about every 4ms.  I understand that I'll
>probably have to interleave the refresh and memory read/write cycles, but
>I don't know how.  If anyone can give me clue as to what kind of scheme I
>should use for this, let me know.  I have 3 clocks available to use in my
>system for the refresh cycle: 640000Hz, 320000Hz and 40,000Hz.  I figure
>it would be best to use the first one, but even if I do all the refresh
>at once, I'd still end up with a gap in the sound and some of the memory
>going bad.  How do they do it in those tapeless answering machines?

Its a long time since I played with DRAMS, but I would think that with 
a bit of judicious programming you may be able to avoid a refresh 
circuit. As long as you access all rows (columns?) within 4 ms the ram 
gets refreshed, so while you're recording you'll be refreshing anyway, 
ditto for playback. The rest of the time you could possibly arrange an 
interrupt routine every 4 mS to just read the necessary number of 
addresses if you can't build it into your program. If this is all B.S. 
then someone please say so :)
bruce
>---
>"See how I LOVE to clean FEEEELTHY CATBOXES!!!!"  -- Ren
>  _____)           ______        _)       _)  EAO102@PSUVM.PSU.EDU
>                               __       __    OPORTO@CORVETTE.ECE.PSU.EDU
>______    ______            ___      ___      Ernie "SHOKK" Oporto
>                               __       __    Computer Lab Attendant
>(_______ _      _ ________ _     _) _     _)  for PSU's CAC Department