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Article #2994Re: SIPP/SIMM hardware Connections: How is it done?
From: Paul Campbell
Date: Fri, 17 Apr 1992 00:25
Date: Fri, 17 Apr 1992 00:25
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Okay, I don't know about emulating a SIMM, but both seem to have the same
pinout. Numerous people responded and filled in the details on some of the
stranger pins (and I lost all the names and addresses, so I can't give credit
where credit is do). The pins are as follows:
From the component side with the card/pin edge facing down, pin 1 is on the
left and 30 is on the right.
The pins are as follows:
1 Vcc 6 IO2 12 A5 18 A9** 24 NC 30 Vcc
2 *CAS 7 A2 13 IO4 19 A10* 25 IO8
3 IO1 8 A3 14 A6 20 IO6 26 DOUT **: NC on 256K SIMMs
4 A0 9 GND 15 A7 21 *WE 27 *RAS *: NC on 256K & 1 Meg
5 A1 10 IO3 16 IO5 22 GND 28 *CAS
11 A4 17 A8 23 IO7 29 DIN
What's up with the second *CAS line, the DIN, and DOUT's, since IO1-IO8
are obviously the bidirectional data lines? It turns out that generating
parity stuff is hard to do with just one data pin, so you got some extra
pins for bit 9 (if it is used).
Compared to a regular 1 meg. or 256K RAM chip, I see no reason why you
can't fake SIMMs, but I can see why you wouldn't WANT TO. The price of
a 1 Meg. SIMM is roughly 35 FRN's, regardless of 8 or 9 bits. The
going price for 1 Meg. RAM chips seems to be roughly 4-5 FRN's. So the
SIMM's are cheaper and smaller. As far as power goes, I wouldn't assume
that they require any less power, but I can't see them drawing any more.
Technical Details
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Newsgroups: sci.electronics,comp.sys.ibm.pc.hardware Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!usc!sol.ctr.columbia.edu!pecampbe From: pecampbe@mtu.edu (Paul Campbell) Subject: Re: SIPP/SIMM hardware Connections: How is it done? Organization: Degrading Chaos, unincorporated References: <1992Apr15.143228.9487@ra.msstate.edu> Message-ID: <1992Apr17.002522.19560@ctr.columbia.edu> Sender: news@ctr.columbia.edu (The Daily Lose) Date: Fri, 17 Apr 1992 00:25:22 GMT Lines: 27