Article View: sci.electronics
Article #8681Re: schmitt trig. nand configurations (HYSTERESIS !)
From: Mark G. Johnson
Date: Mon, 03 Dec 1990 14:33
Date: Mon, 03 Dec 1990 14:33
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(brian l wybaillie) asks whether it is preferable in a *Schmitt* *Trigger*
NAND4 (74xx13) to construct an inverter by tying all 4
input pins to the input signal, or perhaps better to
hook 3 of the 4 inputs to V+ and thereby load the input
signal less.
Shailendra and Marvin (and others) replied that input loading and board
layout concerns should be the deciding factors. However they didn't
address the effect of these connections upon the hysteresis of the gate
{which is presumably the reason Brian is using a '13 instead of a '10}.
The Internal Guts (TM) of the 74xx13 consists of four independent Schmitt
trigger noninverting buffers, followed by a standard TTL NAND gate. So
the four input signals don't mutually interact to set the logic threshold
voltages. Each individual 74xx13 device might, of course, contain some
miniscule fabrication mismatches that would render the trigger voltages
on the 4 Schmitt buffers *slightly* different ... in which case the
Shailendra circuit (3 to VCC, 1 to Input) would have a teencie bit less
hysteresis than the Marvin circuit (4 to Input). It would however be
unwise to depend upon this.
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
(408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!mips!hal!mark From: mark@mips.COM (Mark G. Johnson) Newsgroups: sci.electronics Subject: Re: schmitt trig. nand configurations (HYSTERESIS !) Message-ID: <43743@mips.mips.COM> Date: 3 Dec 90 14:33:05 GMT Sender: news@mips.COM Reply-To: mark@mips.COM (Mark G. Johnson) Organization: MIPS Computer Systems, Inc. Lines: 25