🚀 go-pugleaf

For my microelectronics engineering senior project at RIT, I'm trying 
to create a bonded and etchbacked SOI device using a process similiar 
to S. Nakamura et al. as described in IEDM Technical Digest, '95 (p. 
889).  They created SOI DRAM devices by going through a normal CMOS
process and then flipping it over to bond on a substrate and etching 
away the back side until they were able to isolate the devices, thus
creating SOI devices after fabrication of the devices, as opposed to
buying SOI wafers and then creating the devices on top of that.

I am doing this using RIT facilities.  I want to make an SOI device,
and the advantages to those are many.  My goal is to just make working 
devices.  Here is my process overview:

1. Take prefabricated CMOS device wafers and strip off aluminum and 
oxide.

2. Coat with BPSG glass

3. CMP the glass.

4. Take bare silicon wafer, and coat with BPSG glass.

5. Place bare wafer on top of device wafer in diffusion furnace and
bond both BPSG layers under 800C WetO2 ambient for 10 minutes.

6. Flip the sandwich wafer and grind down backside until 20-50 
microns remain using sandpaper until I can get something better.

7. CMP the backside (which will now become the top)

8. Dry etch the backside until I see LOCOS islands (there is a layer 
of locos islands, leaving about 1000 angstroms underneath silicon

9. Grow 100 angstroms thermal oxide to repair Si damage.

10.  Back end processing.  Must deal with poly contacts...

I need some help specifically on the bonding process.  Can anyone 
give me good references on the actual bonding process, preferably
something that is available over the net?  Will BPSG bond with it 
at that temperature?  What about air pockets?  How do people get 
rid of that?  Is this method safe and cheap?  Will the bonding 
affect the device?  (I will start SUPREME4 simulations next week, 
but in the above paper, they were able to create 64MB dram devices.)

And I have more questions about the backside grinding.  What kind 
of defects can I expect?  (I asked that question at the IEDM 
presentation of the above paper and they said they are now doing 
research on the silicon characteristics.)  Any experts out there
that know if the CMP step can repair crytal defects?  I have to use
a sandpaper or something cheap because we don't have lapping devices.

Again, any references to the above research will help.  Any opinions 
will also be of help.  All will be acknowledged in my paper and 
presentation.

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Bobby Mozumder			For a good time, 
snm6394@vmsmail.rit.edu	        http://www.rit.edu/~snm6394
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