🚀 go-pugleaf

         On the Design of Multi-Valued CCD Circuits
                   By Mostafa Abd-El Barr
                        Room GB 221
                        Time : 12:05
               Date: Friday, March 14th, 1986
                          Abstract

     Multiple-valued logic (MVL) has become the  subject  of
considerable  research  activities.   There  are  two  basic
objectives for using MVL in LSI/VLSI  implementations.   The
first  is  the  possibility of making better use of the chip
area through increased functional density.   The  second  is
the  potential  for reducing interconnection wiring complex-
ity.  Tighter tolerances and reduced noise immunity are  the
major drawbacks of MVL MOS circuits.

     Charge-coupled device (CCD) technology is  amenable  to
binary and MVL digital signal processing and memory applica-
tions.  The technology has the desirable advantages of  high
packing  density,  low  power  consumption and compatibility
with MOS technology, which make  it  suitable  for  LSI/VLSI
implementations.   Its  principal  disadvantages are the low
speed, the need for charge restoration and the need for mul-
tiple clock lines.

     In this seminar we shall consider the MVL design  prob-
lem  for  CCD  circuits.   Synthesis techniques for 4-valued
one- and two-variable functions for CCD  implementation  are
introduced  and shown to give better results than the exist-
ing techniques.  Less expensive realizations  of  basic  MVL
gates using binary CCD gates are also introduced.