Mixing PIII processors with differing cache sizes

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2 total messages Started by GrahamBanks Tue, 31 Dec 2002 19:37

#3222

Author: GrahamBanks
Date: Tue, 31 Dec 2002 19:37

15 lines
2069 bytes

Intel's Processor Specification Update says:

While there are no known issues associated with the mixing of processors
with differing cache sizes in a dual processor
system, and Intel has done nothing to specifically prevent such system
configurations from operating, Intel does not support
such configurations since there may be uncharacterized errata that exist. In
dual processor systems, all processors must be of
the same cache size.

Is anyone aware of any issues with mixing processors with differing cache
sizes? Has anyone successfully done it?

--
Graham

Re: Mixing PIII processors with differing cache sizes

#3223

Author: Jeremy
Date: Wed, 01 Jan 2003 00:00

36 lines
2966 bytes

GrahamBanks wrote:

> Intel's Processor Specification Update says:
> 
> While there are no known issues associated with the mixing of processors
> with differing cache sizes in a dual processor
> system, and Intel has done nothing to specifically prevent such system
> configurations from operating, Intel does not support
> such configurations since there may be uncharacterized errata that exist.
> In dual processor systems, all processors must be of
> the same cache size.
> 
> Is anyone aware of any issues with mixing processors with differing cache
> sizes? Has anyone successfully done it?
> 
> --
> Graham

The cache available on each processor will be equal to the amount of the 
smaller cached proc.  

I think this statement was regarding Xeons...in which case you would be 
wasting alot of money for that unused cache.  With non-Xeon P3s, 
different cache sizes can mean quite different procs with diff FSB speeds. 
For example, you definately don't want to mix 100MHz FSB and 133MHz FSB 
slot1s (which are 512k and 256k cache respectively).

Really you should try to get identical steppings for SMP (look for someone 
selling a matched pair) to ensure they will play nicely together.  Or at 
least check Intel's charts to ensure two different steppings are 
compatible.  

Jeremy
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