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Article #22014

Re: Sanity Check, please

#22014
From: Casey Leedom
Date: Tue, 09 Jan 1990 21:20
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| From: josh@klaatu.rutgers.edu (J Storrs Hall)
| 
| what            1980    1990    extrapolation   2000
| processor
| pins		64	256	x4		1k
| clock		8MHz	32MHz	x4		128MHz
| "Devices"	50k	1M	x20		20M
| mips		1	12	x12		144
| memory(dram)
| bits/chip	16k	1M	x64		64M
| speed		240ns	80ns	/4		20ns

  "pins" and "clock" are the only ones I have an argument with.

  The mechanical insertion force necessary for a 1K pin chip would be
prohibitive if no other considerations came into play.  I think we're
much more likely to see surface mount modules containing CPU, floating
point, memory management, primary- and secondary- cache, high speed bus,
memory and I/O access.  The advanced mounting technology will take
advantage of both sides of the module board(s) and be very small and
dense.  The fancier modules will have provision for multiple busses and
paths to memory and I/O.

  On the clock issue I just think you're way too conservative.  I expect
to see 128MHz within a year to a year and a half.  What the clock speeds
on KMs will be in 2000 I couldn't guess, but they will be faster than
128MHz.

Casey
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From: casey@gauss.llnl.gov (Casey Leedom)
Newsgroups: comp.arch
Subject: Re: Sanity Check, please
Message-ID: <43778@lll-winken.LLNL.GOV>
Date: 9 Jan 90 21:20:08 GMT
References: <Jan.8.22.57.41.1990.234@klaatu.rutgers.edu>
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Organization: Lawrence Livermore National Laboratory
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