Thread View: comp.lang.prolog
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Started by Tong Bo-Ming
Thu, 29 Oct 1992 09:13
Prolog compilers for RISC architectures
Author: Tong Bo-Ming
Date: Thu, 29 Oct 1992 09:13
Date: Thu, 29 Oct 1992 09:13
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Is it possible for Prolog compilers to take advantage of the large number of registers in RISC architectures ? If the compiler is WAM-based, this seems very difficult. Are there any register allocation schemes which can get around this problem ? Tong Bo-Ming bmtong@cs.cuhk.hk
Re: Prolog compilers for RISC architectures
Author: Andrew Taylor
Date: Fri, 30 Oct 1992 20:49
Date: Fri, 30 Oct 1992 20:49
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In article <1992Oct29.091339.20207@cucs5.cs.cuhk.hk> bmtong@cucs11.cs.cuhk.hk (Tong Bo-Ming) writes: >Is it possible for Prolog compilers to take advantage of the large number >of registers in RISC architectures ? If the compiler is WAM-based, this >seems very difficult. Are there any register allocation schemes which >can get around this problem ? Inter-procedural(predicate) register allocation is one way to soak up excess registers. This can be applied in a native code Prolog compiler just has been done with imperative languages. You must take garbage collection into account. Many garbage collectors need to know which registers are valid at the program point at which they have been invoked. This requires passing information describing the "global" registers. The alternative is to use a robust garbage collector but this (I think) would require all stack words to be tagged. I can't see the point in extending the WAM do this but it might be useful in a native code global analysis-based Prolog compiler (see papers by me or by Peter van Roy). Andrew Taylor
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