Article View: comp.lang.verilog
Article #32Re: Getting round verilog hierarchical structure
From: Dan Kegel
Date: Tue, 28 Jul 1992 00:14
Date: Tue, 28 Jul 1992 00:14
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Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes: >Modules in Verilog are organised in a hierarchical structure which, >presumably, is in keeping in line with standard programming practice. >However, I've come up against situations when this rigid structure has >been a problem. >As a simple example, consider the system below in which A, B and C are >modules (representing hardware blocks) with dedicated links to each other. > [ Diagram of A, B, and C, with a signal running from each to each. ] Why not use an overlying module which invokes A, B, and C, and uses module ports for all communication? Seems more egalitarian than putting any of A, B, or C higher or lower. - Dan Kegel (dank@blacks.jpl.nasa.gov)
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!darwin.sura.net!mips!sdd.hp.com!usc!elroy.jpl.nasa.gov!dank From: dank@blacks.jpl.nasa.gov (Dan Kegel) Subject: Re: Getting round verilog hierarchical structure Message-ID: <dank.712282499@blacks.jpl.nasa.gov> Sender: news@elroy.jpl.nasa.gov (Usenet) Nntp-Posting-Host: blacks.jpl.nasa.gov Organization: Image Analysis Systems Group, JPL References: <Bs23x4.330@brunel.ac.uk> Date: Tue, 28 Jul 1992 00:14:59 GMT Lines: 13