Article View: comp.lang.verilog
Article #33Re: Getting round verilog hierarchical structure
From: Bharat P. Savel
Date: Tue, 28 Jul 1992 17:24
Date: Tue, 28 Jul 1992 17:24
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with that kind of instantiations, a performance problem may arise. for instance, we do not know the size of A, B or C. true, it is a great way to go structural, but when the 3 units become very big, speed drops. an alternate way be to have 3 tasks or 3 @always statements. but is this what you want? -- ------------------------------------------------------------------------------- Bharat P. Savel /tmp/Design_Engineer Ext. 1307 Motto: If we can't fix it, it ain't broke
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Path: arc1-ca.pugleaf.net!sparky!uunet!usc!sdd.hp.com!elroy.jpl.nasa.gov!ames!olivea!hal.com!gorn.hal.com!not-for-mail From: savel@hal.COM (Bharat P. Savel) Newsgroups: comp.lang.verilog Subject: Re: Getting round verilog hierarchical structure Message-ID: <153vrlINNkjt@gorn.hal.com> Date: 28 Jul 92 17:24:05 GMT References: <Bs23x4.330@brunel.ac.uk> <dank.712282499@blacks.jpl.nasa.gov> Organization: HaL Computer Systems Inc. Lines: 11 NNTP-Posting-Host: gorn.hal.com