Article View: comp.lang.verilog
Article #34Verilog Synthesis
From: Swaminatha Vasudevan
Date: Wed, 29 Jul 1992 03:05
Date: Wed, 29 Jul 1992 03:05
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Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence? \V
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!stanford.edu!leland.Stanford.EDU!vasu From: vasu@leland.Stanford.EDU (Swaminatha Vasudevan) Subject: Verilog Synthesis Message-ID: <1992Jul29.030523.28537@leland.Stanford.EDU> Sender: news@leland.Stanford.EDU (Mr News) Organization: DSG, Stanford University, CA 94305, USA Date: Wed, 29 Jul 92 03:05:23 GMT Lines: 4