🚀 go-pugleaf

I am trying to include a computer generated casex into a verilog model.
The inclusion was performed painlessly using `include however the casex
has to be included in several places with different statements used in
each place. To get around this the include file has numerous `ifdefs.
My problem is that the `defines stay defined so if I `define a in
module A and b in module B then in effect I get ab in module B. I
guessed that an `undef existed but I couldn't find it in the
documentation so I used strings to scan the executable and found the
keyword, tried inserting `undefs and all worked as I wanted. Now I am
worried about using an undocumented feature and about synthesising. I
am using VERILOG-XL 1.6.0.1 and I wondered if anyone had any comments
on my dilema. BTW basically my only control over the include file is to
post process it, I can't change its format.

Thank you in advance.

-- 

Michael Salmon

#include	<standard.disclaimer>
#include	<witty.saying>
#include	<fancy.pseudo.graphics>

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