Article View: comp.lang.verilog
Article #36Re: Verilog Synthesis
From: Ed Chen
Date: Wed, 29 Jul 1992 08:13
Date: Wed, 29 Jul 1992 08:13
9 lines
807 bytes
807 bytes
In article <1992Jul29.030523.28537@leland.Stanford.EDU> vasu@leland.Stanford.EDU (Swaminatha Vasudevan) writes: >Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence? > >\V COMPASS Design Automation Tools - VLSI Technologies, Phoenix AZ. Ed echen@u.washington.edu
Technical Details
Message-ID:
<1992Jul29.081334.29463@u.washington.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!wupost!usc!sdd.hp.com!uakari.primate.wisc.edu!usenet.coe.montana.edu!news.u.washington.edu!hardy.u.washington.edu!echenReferences:
<1992Jul29.030523.28537@leland.Stanford.EDU>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!wupost!usc!sdd.hp.com!uakari.primate.wisc.edu!usenet.coe.montana.edu!news.u.washington.edu!hardy.u.washington.edu!echen From: echen@hardy.u.washington.edu (Ed Chen) Newsgroups: comp.lang.verilog Subject: Re: Verilog Synthesis Message-ID: <1992Jul29.081334.29463@u.washington.edu> Date: 29 Jul 92 08:13:34 GMT References: <1992Jul29.030523.28537@leland.Stanford.EDU> Sender: news@u.washington.edu (USENET News System) Organization: University of Washington, Seattle Lines: 9