Re: Getting round verilog hierarchical structure

Article View: comp.lang.verilog

Article #37

#37

From: Cindy Eisner
Date: Wed, 29 Jul 1992 07:47

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In article <Bs23x4.330@brunel.ac.uk>, Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes:

> In developing a verilog model, A could instantiate B and C but, as far as
> I can see, this would then mean the link from B to C would not be possible
> as there is no way of directly linking a module to another module which it
> is neither instantiated by nor instantiates.

please elaborate on what you mean by "direct link"?  i don't see any problem
in having a signal between each pair of A-B, A-C, B-C, so i guess this is 
not what you mean.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.

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Path: arc1-ca.pugleaf.net!sparky!uunet!imp!ca41!cindy
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: Getting round verilog hierarchical structure
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Date: 29 Jul 92 07:47:27 GMT
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