🚀 go-pugleaf

I'd like to do the following:

parameter pOW = 27;
parameter [pOW-1:0]  
  Xvob = pOW'b1 << 26;
         ^^^

Apparently, verilog doesn't allow this wanting instead:

  Xvob = 27'b1 << 26;
         ^^

I guess I have to use: 

`define pOW 27
parameter [`pOW-1:0]  
  Kibo = `pOW'b1 << 26;  

I'd been using parameters instead of `defines to avoid
having to use the ` on macro substitutions.  Why does
verilog require the ` ?  This aspect of the language
seems a little ridiculous.

I'd like to get rid of the "26" as well, replacing it with a 
variable so that I can do things like:

i = `pOW-1;
parameter [`pOW-1:0]
  Obik = `pOW'b1 << i; i=i-1;
  Xibo = `pOW'b1 << i; i=i-1;

Oh yeah, I want to take my source into synopsys for synthesis.

Any comments? Ideas?

--
dave
manley@optilink.com