🚀 go-pugleaf

bout three weeks ago I posted the message asking about designing ASIC using
Verilog. So far I  did not receive  many responses.  Any new information or
comments would also be appreciated.


Thanks go to everyone who replied my questions


=============================================================================

I wrote:

We are going to design a ASIC chip. The first problem for us is which design
tools we should use. I have been using SOLO 1400 (a stardard cell design system
of ES2) for several years. Recently, I completed a ASIC design using Cadence
EDGE (V2.1.f.2) and was impressed by the layout quality generated by the
EDGE's placement and route tools. So we have decided that the new ASIC
chip will also be designed using Cadence software, at least the chip layout
should be generated with EDGE's place and route tools. In previous 
design all circuits were entered using schematic entry based on ES2 
standard cell library. I did not have good experience with schematic, 
furthermore, the schematic entry relies directly on certain library, i.e., 
the design is dependent on some IC producer and the technology from the 
very beginning. We think that the new design should be from the very 
first independent on certain IC producer and technology. Instead of schematic
entry we have to use some hardware description language (e.g. Verilog) to 
describe our new chip, moreover, we would like to generate the chip layout 
using Cadence EDGE software again. So our basic consideration:  avoiding
Schematic-entry and Producer and Technolgy independence. I have the following
questions and hope some experters from you could help me:


1. Are there some published papers or books on Verilog language and synthesis 
   from Verilog? I have only a Verilog-XL reference manual at hand, which 
   appears difficult to read for beginner.

2. Are there some converters, which can transform the verilog description 
   into one format which can be used as input data for use with Cadence
   Place and Route tool, e.g. EDIF netlist ?

3. How could I bind the verilog description with some certain library?
   Do IC producers or Cadence provide such "bind" programs (i.e. technology
   mapping)? 


4. Since no schematic exists, how can I simulate the design after the
   final layout (i.e. post-layout simulation)? Are there some extracter,
   which can extract the design to  e.g. SILOS netlist-format, so that I can 
   perform the  simulation and check the simulation results using waveforms ?


5. Some colleagues here are using Xilinx in designing ASIC chips. They would
   like to know whether some tools exists for mapping the verilog description 
   into the fromat for use with Xilinx tools.




=============================================================================


And here are responses:

1. From blacks.jpl.nasa.gov


>3. How could I bind the verilog description with some certain library?
>   Do IC producers or Cadence provide such "bind" programs (i.e. technology
>   mapping)? 
This is done with a logic synthesis package, such as Synopsis'
or Exemplar's products.

>5. Some colleagues here are using Xilinx in designing ASIC chips. They would
>   like to know whether some tools exists for mapping the verilog description 
>   into the fromat for use with Xilinx tools.
Exemplar handles Xilinx, but (sadly) they only accept VHDL input, not
Verilog.
(Write larry@exemplar.com (Larry Lapides) for more info.)


2. From: Jeff Tobin <jefft@hpcvcal.cv.hp.com>

> 2. Are there some converters, which can transform the verilog description 
>    into one format which can be used as input data for use with Cadence
>    Place and Route tool, e.g. EDIF netlist ?
Synopsys can output one of many formats, including netlist EDIF. I'm not sure
if the Cadence routers can handle EDIF, though.
> 
> 3. How could I bind the verilog description with some certain library?
>    Do IC producers or Cadence provide such "bind" programs (i.e. technology
>    mapping)? 
I would recommend using synopsys here. Design in Verilog, using the Synopsys
subset of Verilog, maintaining technology independence, then use synopsys
to synthesize your Verilog HDL into technology-specific gates. 

> 
> 
> 4. Since no schematic exists, how can I simulate the design after the
>    final layout (i.e. post-layout simulation)? Are there some extracter,
>    which can extract the design to  e.g. SILOS netlist-format, so that I can 
>    perform the  simulation and check the simulation results using waveforms ?
This is no different than pre-layout simulation. You'll need a Verilog
simulator. This simulator should have some sort of delay calculator built
in, or added onto it (Verilog-XL comes without a delay calculator, but some
IC vendors may provide a delay calcualtor for their library). Just add the
back-annotated cap values into your design, and you're ready to re-verify
your circuit.
> 
> 
> 5. Some colleagues here are using Xilinx in designing ASIC chips. They would
>    like to know whether some tools exists for mapping the verilog description >    into the fromat for use with Xilinx tools.
I believe that Synopsys recently added support for FPGAs (not sure if Xilinx
was one of the supported vendors), so you could take your technology independentHDL and run it though Synopsys to synthesize a set of FPGAs that perform the
functions of your ASIC. They will not necessarily meet your performance needs,
however.


3. From: marchior@dxcern.cern.ch (Alessandro Marchioro)

 1- Verilog book: look for 
     E. Sternheim et al.
     Hardware Modeling with Verilog HDL
                    Automata Publishing Company
                    POBox 50335
                    Palo Alto  CA 94303
                    fax: (415) 855 9545



4. From: rauletta@sitevax.gmu.edu (R. J. Auletta)


Use VHDL and the Viewlogic Workview tools (in particular their VHDLdesigner
synthesis package.)

The University package/support is very good.

****** Verilog to Xilinx ***********

5. From: Herman Schmit <herman@amc.ece.cmu.edu>


I have written, for my research, a translator that translates a
gate-level subset of Verilog into Xilinx Netlist Format (XNF).  Sadly,
the software we write here is only available to American universities
and companies that fund us.  But I can tell you what I did.

First you need a Verilog parser.  Writing that using yacc and lex for
your chosen Verilog subset shouldn't be that hard.

You have to get info on XNF.  Try to contact Steve Trimberger at
Xilinx.  

        Stephen Trimberger
        Manager, Advanced Development
        Xilinx
        2100 Logic Drive, San Jose, CA 95124
        phone: 408-879-5061
        fax: 408-559-7114.
        I lost his email address.

Xilinx is quite willing to inform interested universities.

Then you have to write a program that takes your Verilog parse tree
and writes out XNF.

 
===========================================================================



Recently, I collected also some information on synthesis using verilog and
VHDL. We heard very different views about Verilog and VHDL. Tow weeks ago 
I installed Verilog-XL simulator and wrote some small programs using Verilog
(Sadly, until now we have not Verilog-Synthesiser), but I have not any 
experience with VHDL (it appears to me that there are many restrictions in 
using VHDL, furthermore, the syntax and program constructs of VHDL seem more 
complex than those of Verilog.) 

Please comment the advantages and disadvantages (or experience) of using
Verilog and VHDL!



Thanks in advance


Xiaoming Fan
Dept. of Computer Science
University of Hamburg
Troplowitzstr. 7 
2000 Hamburg 54
Germany

E-mail: fan@tech7.informatik.uni-hamburg.de