M to Verilog translator

Article View: comp.lang.verilog

Article #64

#64

From: Christian Burisch TT/RKE
Date: Mon, 17 Aug 1992 11:36

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Hi,

Is there an M -> Verilog translator available?
M is the modelling language of Mentor LSIM, 
Verilog is a digital simulator from Cadence.
No support is necessary, any "hack" would be welcome.
Please email to me or post.

Thanks in advance,

Christian

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Message-ID: <1992Aug17.113603.28701@ericsson.se>

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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!ericom!kk293!extchbu
From: extchbu@kk293.ericsson.se (Christian Burisch TT/RKE)
Subject: M to Verilog translator
Message-ID: <1992Aug17.113603.28701@ericsson.se>
Sender: news@ericsson.se
Nntp-Posting-Host: kk293.ericsson.se
Reply-To: extchbu@kk.ericsson.se
Organization: Ericsson
Date: Mon, 17 Aug 1992 11:36:03 GMT
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