🚀 go-pugleaf

From rschop!veritools.com!schop Tue Aug 18 09:52:00 1992
Return-Path: <rschop!veritools.com!schop>
Received: from netcomsv.netcom.com by netcom.netcom.com (4.1/SMI-4.1)
	id AA22377; Tue, 18 Aug 92 09:51:59 PDT
Received: from rschop.UUCP by netcomsv.netcom.com with UUCP (4.1/SMI-4.1)
	id AA06395; Tue, 18 Aug 92 09:51:48 PDT
Received: by veritools.com (4.1/SMI-4.1)
	id AA01070; Tue, 18 Aug 92 09:46:13 PDT
Date: Tue, 18 Aug 92 09:46:13 PDT
From: schop@veritools.com (Robert Schopmeyer)
Message-Id: <9208181646.AA01070@veritools.com>
To: veritool@netcom.com
Status: R

			NEW VERILOG TOOLS FOR VERILOG DESIGNERS 
			___________________________________
8/17/92
	VERITOOLS INC. has several new software products for designers
	using Verilog which make Verilog easier to use and allow the user
	of Verilog to be more productive. 

	Undertow I, the wave display program for Verilog Value Change 
		    Dump Files, engineers using this program have been 
		    getting 5 times the productivity over previous
		    ways of debugging simulations

	Typetool I, an easy to use graphical front-end for Verilog
	
	VLTool, a graphical front-end for Verilog with a design parser

	Vflat I, the Verilog netlist flattener

	These products are available for use on Sun-Sparc workstations and 
	are obtainable with ftp anonymous.  Undertow I is also available for use
	on the HP 700 workstations. Please contact Veritools Inc. directly
	for this version.

	Other products available from Veritools Inc. are:

	Nettool, a tool to automatically determine the status of all of the 
	available workstations on your network and allow the user to log
	into the most appropriate one

	veriLINT, a program to lint your Verilog code for user selectable 
	constructs for both simulation and synthesis 

	Verilog to VHDL converter, converts Verilog code to VHDL code

	interParse, a parser for Verilog, primarily used for syntax checking

	openHDLtoolkit, a software application that reads and parses a Verilog
	HDL description, verifies the syntactic and semantic correctness
	of the description, generates an intermediate representation and 
	provides a comprehensive suite of access routines for manipulating
	this data

 	Veriformal,  a formal verification tool that Boolean compares two
  	representations of a design and determines if they are equivalent or not

	If you would like to retrieve the Veritools' software products using
	ftp anonymous please follow these basic instructions:

		1.  ftp netcom.netcom.com or ftp 192.100.81.100 
	    		 login as anonymous
	   	 	use password as indicated 
		2.  cd pub/veritools
		3.  get veritools_tar.Z
		4.  get README
		5.  close

	If you need any information about these products 
	contact Veritools Inc. at:

		email:  rschop!veritools.com!inquiry@netcom.com
		phone: 415 941-6870
		fax: 415 941-7965
	Verilog is a registered trademark of Open Verilog International.