Thread View: comp.lsi.cad
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Started by Amit Erez
Thu, 21 Jan 1993 08:40
Pin assignment
Author: Amit Erez
Date: Thu, 21 Jan 1993 08:40
Date: Thu, 21 Jan 1993 08:40
42 lines
1853 bytes
1853 bytes
I am in the process of implementing a large project composed of
chips (of various types) packaged in packages (various types) and mounted
on PCB.
Since all the chips are designed in-house, and we have full control
over the process, we are making it in a top-down manner. e.g we start
with a connectivity based placement of the different packages on the PCB,
and by usage of the connectivity we want to assign chips IO signals to the
package pins in a optimized way.
I am looking for a program that can do the job.
- It has to be good enough to respect Vendor constraints (like
input only package pins, pre-assigned tester pins, etc).
- It must be smart enough to consider the situation when a chip
is used more then once on the board, thus not optimizing
differently in each package...
- It should be able to take pre-assigned pins, and complete
the job by respecting it.
- It should be able to use a metrics more complex then
the obvious geometric, where different package inputs pins
have different levels of capacitance.
My questions:
1. Does anybody know of any commercial software that can do that job?
2. Could anybody send me any reference to papers or dissertations which
attack this problem?
Thanks in advance.
---
Amit Erez
Advanced Computer Research Institute Phone: (+33) 72 35 84 59
1, Bld Marius Vivier-Merle Fax: (+33) 72 35 84 10
F-69443 LYON CEDEX 03 Email: amit@acri.fr
Re: Pin assignment
Author: Craig Bender
Date: Mon, 25 Jan 1993 22:08
Date: Mon, 25 Jan 1993 22:08
37 lines
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I don't know of a software tool that can handle your Pin Assignment
problem, but I'll comment on your overall plan.
You're over simplifying by assumming an "in-house design" provides
"full control over the process" (of assigning pin locations) since
who manufactures the ICs and who within your company approves spending
(money) are going to limit `your control'. For example:
1] All Gate-Array ASIC suppliers have a limited number of package
options available and many packages have limitations on power
and ground locations. This is very true of high pin count
ceramic packages.
2] If you're generating the packaged units in-house then your purchasing
folks will want `open-tooled' packages selected instead of custom
designs that can cost $45K+ to design and tool.
3] Even if all the ICs are in PQFPs with no PQFP Vendor restrictions
on pin assignments you'll still have pin placement restrictions due
to the actual IC functions.
IC -a- could be designed on a FAB process and set of design rules that
requires one power/ground pair per every eight output pads while IC
-b- needs one pair per four outputs. If both devices have the same
footprint and drive the same bus you're going to be hard pressed to
find a single solution.
These are real world issues and very dependant on the IC functions,
design rules, and process performance while they have less to do with
`in-house design and control' of the ICs themselves. ASIC package selection
is still treated as a low-tech no brainer that causes endless confusion
for IC designers and ASIC suppliers (like me) late in a design cycle.
Good Luck.
Craig Bender
Product Engineer
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