🚀 go-pugleaf

dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
: I've been looking for an appropriate newsgroup in which to discuss
: board test and related topics and it seems that this is the closest
: that there is. Sci.electronics is too general and has too much flow,
: but comp.lsi.testing seems to have appropriate discussion (at least
: on 1149), and would like to see if other individuals agree (or

Are there any LSI parts on the board?  Do VLSI parts cound as LSI?
How about some really big MSI parts? How about a 74bct8374?

Given that USENET is an anarchy, I guess my vote counts.

Albert Alcorn
Hewlett Packard
Semiconductor Systems Center
Digital IC Test products
(408|T) 553-7482
albert@sc.hp.com

dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
....
>Anyway, let me know if I'm off-base here or what.

>Regards, Doug

You are more than welcome to comp.lsi.testing.  In fact 1149.1 is 
exactly why I came here a few weeks ago.  There was considerable
response to my request for experince on the topic of boundary-scan,
and by judging the responses I received, you will find no better
forum to ask such questions.  Apparently this is where the 1149.1 
experts occasionally hang out.

For those that may be wondering, I'm still digesting all the 
information I was sent.  I've gone ahead and set up in-house demo's 
with TI and Fluke/Philips.  I've spoken with Alpine Image Systems, 
National Semiconductor, Teradyne, Tektronix...

I ordered and received some books from IEEE.  "The Test Access Port
and Boundary Scan Architecture" by Maunder and Tulloss,  and also
"Integrating Design and Test: Using CAE Tools for ATE Programming"
by Ken Parker, so I've been busy reading.

So Doug, While I'm trying to formulate my next question, let's hear 
one from you!  Have you had any 1149.1 implementations tossed your way
in board test.  Did your testers handle the task.  Who wrote the b-scan
test vectors?  Did you have any internal scan paths?  Multiple paths?
What where the major hurdles?  Did anything go completely wrong?

Anyone else...?

Ed Kearns
BBN Systems & Technologies
Bellevue, Washington
206-957-3271

In article <1992Nov18.170306.4244@titan.ksc.nasa.gov>, dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
|> I've been looking for an appropriate newsgroup in which to discuss
|> board test and related topics and it seems that this is the closest
|> that there is. Sci.electronics is too general and has too much flow,
|> but comp.lsi.testing seems to have appropriate discussion (at least
|> on 1149), and would like to see if other individuals agree (or
|> disagree). I've been in board test for ~12 yrs with 6 on the 
|> genrag 1296 functional tester and the last 6 on an hp3065at.
|> 
|> Anyway, let me know if I'm off-base here or what.
|> 
|> Regards, Doug
|> 
|> -- 
|> +-----------+---------------------------------+--------------------------+
|> | Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
|> +-----------+----+---------------------------++--------------------------+
|> | Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |

	For what it's worth, I think this is a perfectly appropriate forum for
discussing board test related issues. Unless you want to start up an new 
"comp.lsi.board.testing" group or something :-). 

Regards;

Maitreya (just my .02 worth) Sengupta.

>So Doug, While I'm trying to formulate my next question, let's hear 
>one from you!  Have you had any 1149.1 implementations tossed your way
>in board test.  Did your testers handle the task.  Who wrote the b-scan
>test vectors?  Did you have any internal scan paths?  Multiple paths?
>What where the major hurdles?  Did anything go completely wrong?
>
>Anyone else...?
>
>Ed Kearns

Ed:
So far we haven't had any 1149.1 designs come our way. I don't think
that the design guys in NASA have really gotten into it yet... they
are using XiLinx and Altera stuff to keep us pretty busy and I'm not
sure that if they started using 1149.1 chips whether they would write
on-board code for BIT or just for us board test people to crank out 
quicker tests. BTW, our board test equipment is being used for depot /
interlevel repair of broke boards that used to work. So 1149.1 tests
would be good for getting up a quick test of the board, but later 
(as time allows or testing requires) it would behoove us to write a 
more complete test. The built-in RAM tests that HP provides with the
tester tests a minority of addresses, and while that ok for the 
manufacturing environment looking for incorrectly mounted or dead chips
in quick test time, doesn't provide a thorough test in the depot 
environment.

Major hurdles? Getting design to put in gates to disable ttl
oscillators... :^) ... no flame intended. All things considered
we actually have a pretty good rapport with the design people.

Regards, Doug

-- 
+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
+----------------+---------------------------+---------------------------+

>In article <1992Nov18.170306.4244@titan.ksc.nasa.gov>, dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
>|> stuff deleted...
>|> genrag 1296 functional tester and the last 6 on an hp3065at.
           ^^^^-- should be 1796 tester. Ah, good, at least I'm
                  starting to forget!
>|> Regards, Doug

-- 
+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
+----------------+---------------------------+---------------------------+

In article <lglr0dINN5oj@news.bbn.com> ekearns@bbn.com (Edward Joseph Kearns) writes:
>
>You are more than welcome to comp.lsi.testing.  In fact 1149.1 is 
>exactly why I came here a few weeks ago.  There was considerable
>response to my request for experince on the topic of boundary-scan,
>and by judging the responses I received, you will find no better
>forum to ask such questions.  Apparently this is where the 1149.1 
>experts occasionally hang out.
>
   Great! I'm glad to see some talk about board test here.

>I ordered and received some books from IEEE.  "The Test Access Port
>and Boundary Scan Architecture" by Maunder and Tulloss,  and also
>"Integrating Design and Test: Using CAE Tools for ATE Programming"
>by Ken Parker, so I've been busy reading.
>
    Ken Parker has a new book out, _The Boundary Scan Handbook_.  It's
published by Kluwer, and I think it's pretty good.  I can post my
review of it here if people are interested.

Regards, Dan
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