🚀 go-pugleaf

some useful references:

	How to Avoid Synchronization Problems
	Peter Stoll, Intel
	VLSI DESIGN
	Nov-Dec 1982

	On the Synchronization of a Microprocessor
	Chao et al. IBM
	IEEE Proceddings of the CICC 1986 pp447-450

	The Behavior of Flip-Flops Used as Synchronizers...
	H. J. Veendrik
	IEEE  Journal of Solid State Circuits Vol  SC15
	april 1980 pp 169-175

In general, Gate array and standard cell flip-flops have
an inherent problem, they are designed to minimize area, and as a result
suffer from meta-stability and setup-and hold problems.

From my experience the best synchronizer element for an ASIC 
design would be the a 7474 flip-flop that is implemented as a "hard-macro",
ie placed and routed as one unit.

It is important that the flip-flop is implemented as cross-coupled
nand or nor gates and the outputs from the ff are buffered.

many ASIC flip-flops are implemented using master-slave latches,
these are very dense but would not meet your requirements.

Some other tricks can be played using parrelel synchronizers and
a voting scheme, with different delay elements inserted before
each synchronizer. This method does not suffer from the 
latency of a multiple cascaded flip-flop implementation.


-- 
Michael Upton@Seattle Silicon (uucp: ...uw-beaver!tikal!ole!upton)
/*           Semi-conducting our business since 1983        */