🚀 go-pugleaf

David T. Wang (veakblad@Glue.umd.edu) wrote:
: Tae Song (tsong@erols.com) wrote:
: :The 60-90 mHz 601s were created using IBM's 0.5 micron 4-metal-layer process.
: :The higher clocking 601s and 603s were created using IBM's .5 micron 5-metal-
: :layer process.  The five-metal-layer process allowed IBM to pack more 
: :transistors into a smaller area and increase the speed.

: This then begs the question, what exactly does IBM manufacture on its .35 
: micron process?  I recall that Intel made a big hoopla about fabbing the
: 120 MHz Pentium on the .35 micron process back near the end of 1994, and 
: a bunch of people (including me) assumed that Intel had then surpassed 
: IBM in the process technology game and reached .35 micron first.  This
: turned out to be incorrect. IBM later revealed that it had actually 
: fabricated some shipping chips on its .35 micron process tech (albeit a
: relatively small quantity) about 3 month before Intel did.  Now Intel is
: just about all converted to the .35 micron process, judging by the number 
: of 133, 15 and 166 MHz chips it's pumpimg out, but IBM seems to be still
: manufacturing on the .5 micron process, with no move insight to move to
: the CMOS5X .35 micron stuff until 604e.  (I still haven't found out for
: certain what the 150 MHz 604 is fabbed on, microprocessor reports and
: IBM's web site contracdict each other here)

Aha, I think that I've found the answer.  The answer is that IBM calls 
a couple of different process technology all as .5 micron process.
Have a look at ...
http://www.chips.ibm.com/technology/index.html

IBM actually has two different " 0.5 micron process technology" (okay,
at least two, probably more) on this page it shows CMOS5L and CMOS5S.
and if we go into more details about CMOS5L and CMOS5S, we find that
CMOS5S has a .36 um effective channel length, and was probably the 
technology which 601 was fabbed on.  No doubt that the PPC604@150 was
fabbed on CMOS5S, and the slower parts could be from a CMOS5L process,
and IBM could still call them all "0.5 micron process"  This is 
probably where the confusion was introduced, as Microprocessor Reports
may have just looked at it, and just said, okay, the 601 and the 604
has reached .35 micron, whereas if you just looked at IBM's page without
digging into the details, you'd think that they're all still at .5 
micron.  Maybe the CMOS5S could be described as a 0.4 micron process?
it's defintely more advanced, and you can pack more gates onto the
chip, as compared to CMOS5L.  This would have at least solved my confusion.

Okay, now, still more question, what, other than the 133 MHz Cyrix 6x86 chip,
does IBM fab on its CMOS5X process? (.31 um effective channel length)

David T. Wang wrote:
> 
> David T. Wang (veakblad@Glue.umd.edu) wrote:
> : Tae Song (tsong@erols.com) wrote:
> : :The 60-90 mHz 601s were created using IBM's 0.5 micron 4-metal-layer process.
> : :The higher clocking 601s and 603s were created using IBM's .5 micron 5-metal-
> : :layer process.  The five-metal-layer process allowed IBM to pack more
> : :transistors into a smaller area and increase the speed.
> 
> : This then begs the question, what exactly does IBM manufacture on its .35
> : micron process?  I recall that Intel made a big hoopla about fabbing the
> : 120 MHz Pentium on the .35 micron process back near the end of 1994, and
> : a bunch of people (including me) assumed that Intel had then surpassed
> : IBM in the process technology game and reached .35 micron first.  This
> : turned out to be incorrect. IBM later revealed that it had actually
> : fabricated some shipping chips on its .35 micron process tech (albeit a
> : relatively small quantity) about 3 month before Intel did.  Now Intel is
> : just about all converted to the .35 micron process, judging by the number
> : of 133, 15 and 166 MHz chips it's pumpimg out, but IBM seems to be still
> : manufacturing on the .5 micron process, with no move insight to move to
> : the CMOS5X .35 micron stuff until 604e.  (I still haven't found out for
> : certain what the 150 MHz 604 is fabbed on, microprocessor reports and
> : IBM's web site contracdict each other here)
> 
> Aha, I think that I've found the answer.  The answer is that IBM calls
> a couple of different process technology all as .5 micron process.
> Have a look at ...
> http://www.chips.ibm.com/technology/index.html
> 
> IBM actually has two different " 0.5 micron process technology" (okay,
> at least two, probably more) on this page it shows CMOS5L and CMOS5S.
> and if we go into more details about CMOS5L and CMOS5S, we find that
> CMOS5S has a .36 um effective channel length, and was probably the
> technology which 601 was fabbed on.  No doubt that the PPC604@150 was
> fabbed on CMOS5S, and the slower parts could be from a CMOS5L process,
> and IBM could still call them all "0.5 micron process"  This is
> probably where the confusion was introduced, as Microprocessor Reports
> may have just looked at it, and just said, okay, the 601 and the 604
> has reached .35 micron, whereas if you just looked at IBM's page without
> digging into the details, you'd think that they're all still at .5
> micron.  Maybe the CMOS5S could be described as a 0.4 micron process?
> it's defintely more advanced, and you can pack more gates onto the
> chip, as compared to CMOS5L.  This would have at least solved my confusion.
> 
> Okay, now, still more question, what, other than the 133 MHz Cyrix 6x86 chip,
> does IBM fab on its CMOS5X process? (.31 um effective channel length)

Probably PPC.  IBM will be officially announcing CMOS 6 process this year
(.20 um effective channel length).  Of course all this is total meanless.
It's how fast and cheap you can make a CPU that really counts and I feel IBM
has a strong edge with their design/process.

The P6 is a bloated pig and Intel's just throwing more silicon to keep from
falling behind (i.e. 604's 3.6 million transistors to 5.5 million in the P6.)
And that's not including the internal 256K/512K L2 cache. (512K in the 200 mHz
P6) 

x86 archtecture peaked with the P5 and heading into it's twilight years with
P6. The P7 will probably be a joke... Intel's supposely working on two versions,
one of which they are working with HP (which will handle PA-RISC and X86
instructions) and one that is being developed internally and handles x86
instructions only.

As far I can tell, VLIW will probably end up being software/hardware scheduling
system. Software hinting the direction of branches/resolving dependencies and
hardware making the final decisison at run time.  Not too much difference from
the current state of affairs with compilers for superscalar CPU, I'd imagine.

If they acheive their 2 billion ops/sec goal it will likely come from higher clock
speed than anthing else.  I think Intel and HP are only working together to "borrow"
some technologies to improve their own respective CPU designs.

That's my opinion anyways.

Tae Song (tsong@erols.com) wrote:
: David T. Wang wrote:
: > 
: > Okay, now, still more question, what, other than the 133 MHz Cyrix 6x86 chip,
: > does IBM fab on its CMOS5X process? (.31 um effective channel length)

: Probably PPC.  IBM will be officially announcing CMOS 6 process this year
: (.20 um effective channel length).  Of course all this is total meanless.
: It's how fast and cheap you can make a CPU that really counts and I feel IBM
: has a strong edge with their design/process.

Apparently not the PPC, with the possible excepion of PPC604@150 and the 
PPC601+.  I honestly don't believe that any PPC will be fabbed on that
.2 um process mentioned above, but it has been bounced around that
the upcoming PPC604e's will be fabbed on the .25 micron process.  IBM
still have an edge with the process technology, but they don't have any
significant volume with the bleeding edge process technology. 

: The P6 is a bloated pig and Intel's just throwing more silicon to keep from
: falling behind (i.e. 604's 3.6 million transistors to 5.5 million in the P6.)
: And that's not including the internal 256K/512K L2 cache. (512K in the 200 mHz
: P6) 

Sorry, I'd have to disagree (naturally) There is no P6 with the 512K cache 
at this time. the only announced "512K" version is the 166 MHz version, 
for the server market, though that version still hasn't shipped yet (to my
knowledge)  P6 does have a lot of transistors, but I don't think that 
you'll hear many people call the Dec Alpha 21164 bloated. it's got 9.3
million transistors on the same die.  Die size wise, the 200 MHz P6 is
smaller than PPC604-100, 120 and 133 (194 mm^2 vs 196 mm^2)

: x86 archtecture peaked with the P5 and heading into it's twilight years with
: P6. The P7 will probably be a joke... Intel's supposely working on two versions,
: one of which they are working with HP (which will handle PA-RISC and X86
: instructions) and one that is being developed internally and handles x86
: instructions only.

You are quite mistaken, there is no such thing as a 64 bit x86 instruction.
(not counting MMX ofcourse) Intel's version will indeed "handle" the 
newer 64 bit ISA.  Will the Intel chip handle PA-RISC? I don't know,
I haven't seen anything leak out on this subject. 

: As far I can tell, VLIW will probably end up being software/hardware scheduling
: system. Software hinting the direction of branches/resolving dependencies and
: hardware making the final decisison at run time.  Not too much difference from
: the current state of affairs with compilers for superscalar CPU, I'd imagine.

possibly, the papers I've read on VLIW suggest that it'll be difficult to scale
in the conventional manner we've been familiar with.  However, Intel/HP has
already stated that the P7 will be "Post RISC and Post VLIW"  So, it won't 
be any classical VLIW or RISC design (what the post thing means, I have no idea)
What I do know is that if someone wants to build a classical VLIW machine,
some of the scalability problems  could be solved with dynamic recompilers,
which could be built into the OS, so it's not an impossible task. So what's
the advantage you may ask? well, if we do get the advertised speedup, then
a new OS with a dynamic recompiler would be worth the trouble. (OTOH, if
the speedup isn't any better than a Dec Alpha per se, it'll be just a lot of 
hooey)

: If they acheive their 2 billion ops/sec goal it will likely come from higher clock
: speed than anthing else.  I think Intel and HP are only working together to "borrow"
: some technologies to improve their own respective CPU designs.

: That's my opinion anyways.

yes, "borrow".  However, everyone "borrows" from someone else. It has been
pointed out that all the "new" concepts contained in P6, like Out of Order 
execution, are all concepts that mainframe designers employed a good 20 to 30 
year ago.  Even VLIW is a good 20 years old.  The difficulty is in deciding
which technology to "borrow" and implement a state of the art CPU. 

David T. Wang (veakblad@Glue.umd.edu) wrote:
: Sorry, I'd have to disagree (naturally) There is no P6 with the 512K cache 
: at this time. the only announced "512K" version is the 166 MHz version, 
: for the server market, though that version still hasn't shipped yet (to my
: knowledge)  P6 does have a lot of transistors, but I don't think that 
: you'll hear many people call the Dec Alpha 21164 bloated. it's got 9.3
: million transistors on the same die.  Die size wise, the 200 MHz P6 is
: smaller than PPC604-100, 120 and 133 (194 mm^2 vs 196 mm^2)

Compared to the Pentium or PentiumPro, the Alpha 21164A/300 is a sleek 
SOB.  Its has 9.3 million transistors because it has both a 8KB direct 
mapped AND a 96KB level 2 cache right on the same piece of silicone.

BTW, the Pentium Pro's LV 2 cache is not on the same silicon slice with 
the rest of the CPU, rather, it is only sharing the same package. 

: : If they acheive their 2 billion ops/sec goal it will likely come from higher clock
: : speed than anthing else.  I think Intel and HP are only working together to "borrow"
: : some technologies to improve their own respective CPU designs.

: : That's my opinion anyways.

: yes, "borrow".  However, everyone "borrows" from someone else. It has been
: pointed out that all the "new" concepts contained in P6, like Out of Order 
: execution, are all concepts that mainframe designers employed a good 20 to 30 
: year ago.  Even VLIW is a good 20 years old.  The difficulty is in deciding
: which technology to "borrow" and implement a state of the art CPU. 

Digital Equipment plans to have the Alpha pushed out past 1 GigaHerz by 
the year 2000, and even SGI/Mips/Cray plan to be at least a full step 
ahead of anything Intel puts out (the P6/150 only does 215 SPECfp while a 
MIPS R10000 does around 600 SPECfp).  True that Intel puts more focus into 
Integer math while MIPS put its focus in Floating Point, but the fact 
remains...  now that SGI is running things a lot more over at MIPS, I 
can't wait to see what they have in store for us with the R12000.


But he is correct by saying "borrow".  When I look at the specs for all 
workstation RISC based CPUs, the HP-PA is the 2nd slowest (only the PPC620 
is slower).  The odd thing is that in dollar volume, the HP-PA line sold 
the most.  Why is it that the worst CPUs always sell the best?  Hmmm... 
Anyways, I fear that both will snag stuff from other chip makers.  I see 
the design of something close to the 'Visual Instruction Set' that the 
UltraSparcs use, or some kind of new instruction sets designed to handle 
specific jobs.

                       Greg Baldwin (drizzit@eskimo.com)
     Amiga junkie and user since 1987    Computer Science & DTV Student
     Commodore64 fan since about 1983    http://www.eskimo.com/~drizzit
               Tyranical EFNet #Amiga Channel Operator "Drizzit"