interrupt handling on the Symmetry system

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2 total messages Started by George Bier Mon, 27 Mar 1989 17:47

#791

Author: George Bier
Date: Mon, 27 Mar 1989 17:47

16 lines
1123 bytes

I am hoping someone could enlighten me on how a processor is selected for
handling interrupts on a Symmetry system.  I believe that on the Balance
system, the SLIC interface was used to select the processor currently running
the lowest priority process.   What is done on the newer machines?   In 
addition, if you happen to know how other multiprocessors systems besides 
the Symmetry (for example Alliants) select the processor to handle an 
interrupt, I would appreciate hearing about that too.  Any references 
would also be appreciated.

thanks,

--george

Internet:	bier@cs.wisc.edu
UUCP:   ...!{harvard,seismo,topaz,akgua,allegra,usbvax}!uwvax!bier

Re: interrupt handling on the Symmetry system

#793

Author: Phil Hochstetler
Date: Tue, 28 Mar 1989 16:57

19 lines
1487 bytes

In article <7367@spool.cs.wisc.edu> bier@cottage.cs.wisc.edu (George Bier) writes:
| 
| I am hoping someone could enlighten me on how a processor is selected for
| handling interrupts on a Symmetry system.  I believe that on the Balance
| system, the SLIC interface was used to select the processor currently running
| the lowest priority process.   What is done on the newer machines?   In 
| addition, if you happen to know how other multiprocessors systems besides 
| the Symmetry (for example Alliants) select the processor to handle an 
| interrupt, I would appreciate hearing about that too.  Any references 
| would also be appreciated.

SYMMETRY systems use the same mechanism as the BALANCE system does in
regards to handling interrupts.  The biggest performance changes are
from using the 386 at a higher clock rate instead of the 32032, copy
back cache, and going to memory based locks (instead of the SLIC).

Phil Hochstetler		UUCP:  uunet!sequent!phil
Sequent Computer Systems
Beaverton, Oregon

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