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In article <713099311.0@halluc.com>, Michael.Malak@halluc.com (Michael Malak) writes:
>I found the recent article in the August/September issue of Circuit Cellar Ink
>about DSPs vs. RISC very interesting.  In it the i860 is benchmarked as being
>the fastest at 96-tap FIR filtering.  It was compared against the Am29050, the
>C30, the 56001, the 96000, and a few others.  But that's as far as the article
>went -- it did not compare performance for doing FFTs.
>
>Does anyone have any information about how fast the i860 can do an FFT, either
>theoretical or measured?  I'm especially interested in how it compares against
>the C30, the 96000 and the 56001.  Because since there don't seem to be any 386
>or 486 motherboards out there with DSPs on them, the one from Happauge with the
>i860 on it might be worth a look.
>

If the following two conditions are met:

	1. All your data occupies less than 8 kbytes (such that all data
	   is in the cache or in registers)
	2. Your algorithm is such that it can be implemented in i860
	   pipelined mode (which is awkward to program)

then the i860 is a winner. Otherwise, it's a loser (if you compare with
dedicated DSP's). Non-pipelined mode is 3-4 cycles per instruction, memory
bandwidth is one access per two cycles, if my memory serves me right.

-- 
***** hlj@hal.nta.no (Harald Ljo"en) expressing his private opinions ******

Michael.Malak@halluc.com (Michael Malak) writes:

[...stuff deleted...]

>Does anyone have any information about how fast the i860 can do an FFT, either
>theoretical or measured?  I'm especially interested in how it compares against
>the C30, the 96000 and the 56001.  Because since there don't seem to be any 386
>or 486 motherboards out there with DSPs on them, the one from Happauge with the
>i860 on it might be worth a look.

I have seen advertised numbers from several i860 based array processor 
vendors in the range of 0.75 to 0.8 msec for a 1024-pt complex FFT.
Although I have not timed FFT code on the i860, I believe these numbers
are reasonable.

An EDN article in the 7 November 91 issue has a comparison of various
32-bit floating point DSP's, including FFT benchmarks.  Unfortunately,
I believe this article misquotes the i860XP performance, listing it
as 76 msec instead of the more reasonable value of 0.76 msec for the
1024-pt complex FFT.  A word of caution though, these numbers are only 
achievable with hand-coded routines. 

Miguel Oyarzun
moyarzun@bbn.com

As you may recall, On 6 Aug 92 05:00:00 GMT, Michael.Malak@halluc.com (Michael Malak) said:

Michael> I found the recent article in the August/September issue of Circuit
Michael> Cellar Ink about DSPs vs. RISC very interesting.  In it the i860 is
Michael> benchmarked as being the fastest at 96-tap FIR filtering. [...]

This is believable. The 860 has an 8Kbyte on-chip cache (like the 486, I think)
and this is a nice place to store filter coefficients (taps).  Additionally, the
floating-point side of the 860 is essentially a 3-stage multiply pipeline
followed by a 3-stage add pipeline. So you just do 3 points at a time and you
can make a real-valued FIR filter scream. (Complex is quite a different story -
three-stage pipelines make things messy).

Michael> Does anyone have any information about how fast the i860 can do an FFT,
Michael> either theoretical or measured?  I'm especially interested in how it
Michael> compares against the C30, the 96000 and the 56001.  Because since there
Michael> don't seem to be any 386 or 486 motherboards out there with DSPs on
Michael> them, the one from Happauge with the i860 on it might be worth a look.

In the 860 bible (i860 Microprocessor Architecture by Neil Margulis), the author
codes an FFT which achieves 57/80 MFlops. This is not really what the beast is
designed to do, IMHO. Seems I'm always writing 3 different versions of the same
routine - one for extremely short vectors (throw everything in registers), one
for medium-sized "if it all fits in cache" vectors, and one for long vectors
that use pipelined memory loads, bypassing the cache because they would just
thrash. I suspect I'd wind up doing much the same if I were coding an FFT, which
I haven't [as yet] had to do.

Hope this helps.
--
        Alan J.Stein    MIT/Lincoln Laboratory    alans@ll.mit.edu

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In article <1992Aug6.125445.10704@nntp.nta.no> hlj@hal.nta.no writes:
>
>If the following two conditions are met:
>
>	1. All your data occupies less than 8 kbytes (such that all data
>	   is in the cache or in registers)
		Obviously, you don't know about the existence of the nex-gen
		860 which has 16K of data/instr cache. There are some other
		instr enhancements like 'pfld.q' to make use of full b/w.

>	2. Your algorithm is such that it can be implemented in i860
>	   pipelined mode (which is awkward to program)
		To get peak performance, you have to program most uP in 
		assembly language. There is no doubt that the i860 pipeline
		is hard to follow, but once you get the hang of it, its fairly
		easy..............

>
>***** hlj@hal.nta.no (Harald Ljo"en) expressing his private opinions ******


--
____________________________________________________
Ravi S. Rao
SP1-82	Intel Corpn, Chandler, AZ

e-mail: rrao@hopi.intel.com, rrao@pima.intel.com
____________________________________________________

In article <12948@inews.intel.com> rrao@pima.intel.com (Ravi Rao) writes:
>		To get peak performance, you have to program most uP in 
>		assembly language. There is no doubt that the i860 pipeline
>		is hard to follow, but once you get the hang of it, its fairly
>		easy..............
That's pretty lame.  Most RISC chips with the latest compiler technology
can do better than most assembly langauge programmers.....the compilers
don't do anything that humans can't do but it's a lot easier for a good
compiler to reuse registers and explore all the different possibilities.

Has anybody compared current RISC chips (R4000, HP's new machine, RS6000,
DEC's alpha) to the DSP chips?  DSP chips might be cheaper since you don't
need fancy memory management but it no longer seems clear to me that 
DSP chips are that much faster.

								Malcolm

> Most RISC chips with the latest compiler technology can do better than
> most assembly langauge programmers.

That entirely depends on the chip, the compiler, and the algorithm being
implemented. The above statement seems to be true sometimes, but 
absolutely not all of the time. What kind of FFT time do you get with
a more traditional RISC architecture such as a R3000 (a RISC with a 
hot compiler) ? Is the odd-ball architecture of the i860 justified by
its improved performance ?

	Jeff Enderiwck
	jeff@dsp.sps.mot.com

In article <12948@inews.intel.com> rrao@pima.intel.com (Ravi Rao) writes:
| In article <1992Aug6.125445.10704@nntp.nta.no> hlj@hal.nta.no writes:
| >
| >If the following two conditions are met:
| >
| >	1. All your data occupies less than 8 kbytes (such that all data
| >	   is in the cache or in registers)
| 		Obviously, you don't know about the existence of the nex-gen
| 		860 which has 16K of data/instr cache. There are some other
| 		instr enhancements like 'pfld.q' to make use of full b/w.
	Hmmm, seems like DSPs or RISC uPs which can efficiently access external
	memory (low access latencies and burst modes, >1 i/o bus for DSPs)
	would have an advantage over large *expensive* on-chip caches.  Just
	how expensive is this new gen 860? ;v)

| >	2. Your algorithm is such that it can be implemented in i860
| >	   pipelined mode (which is awkward to program)
| 		To get peak performance, you have to program most uP in 
| 		assembly language. There is no doubt that the i860 pipeline
| 		is hard to follow, but once you get the hang of it, its fairly
| 		easy..............
	860 programs must be hand-coded to get anywhere near stated
	performance.  Most RISC processors (the 860 is a VLIW uP, *not* RISC)
	perform quite well using compiled C.  For DSP, RISC can be easily hand
	programmed - the superscalar varieties even do the scheduling (with
	small scale optimizations) for you (unlike the 860).

Disclaimer:  I speak for myself and no one else - hell, I don't even work with
the Am29050 floating point RISC microprocessor any more.
--
Paul R. Teich                          pteich@cayman.AMD.COM
Advanced Micro Devices, Inc.           Direct 1-512-462-4268
5900 E. Ben White Blvd., MS 561        WATS   1-800-538-8450 x54268
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