Impact of minimal transistor width 3 or 4 instead of 2?

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3 total messages Started by Ronald Hindmarsh Mon, 25 Jan 1993 19:54

#687

Author: Ronald Hindmarsh
Date: Mon, 25 Jan 1993 19:54

18 lines
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I am working on a CMOS-VLSI layout generator for digital circuits. 

For topological reasons I would like to limit the MINIMUM w/l
of a MOS transistor to 3 or 4 (in some physical design rules
of a process I have seen a minimal transistor width of 2).

Do you think, from your experience, this would have a strong
impact on the performance or the power consumption of a circuit?


----------------------------------------------------------------------
 Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: (+49) 30 314-73432
 W-1000 Berlin 10                             Fax: (+49) 30 314-21103
----------------------------------------------------------------------

Re: Impact of minimal transistor width 3 or 4 instead of 2?

#699

Author: Brian A. Blow
Date: Tue, 26 Jan 1993 14:33

22 lines
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Ronald Hindmarsh (ronald@cs.tu-berlin.de) wrote:

: I am working on a CMOS-VLSI layout generator for digital circuits. 

: For topological reasons I would like to limit the MINIMUM w/l
: of a MOS transistor to 3 or 4 (in some physical design rules
: of a process I have seen a minimal transistor width of 2).

: Do you think, from your experience, this would have a strong
: impact on the performance or the power consumption of a circuit?

Using wider transistors will mean that you will have to drive larger
gate capacitances.  This will lead to a slightly increased power consumption.

If you use wider transistors to drive these gates, you will have a
greater charging/discharging current to do this, so circuit speed should 
not significantly change.


Brian Blow                         brian.blow@medtronic.com
Medtronic, Inc.                    (612) 574-4030
Minneapolis, MN

Re: Impact of minimal transistor width 3 or 4 instead of 2?

#693

Author: Paul Cohen
Date: Thu, 28 Jan 1993 02:23

23 lines
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In article <1k1gi3INNbgs@news.cs.tu-berlin.de> ronald@cs.tu-berlin.de (Ronald Hindmarsh) writes:
>
>I am working on a CMOS-VLSI layout generator for digital circuits. 
>
>For topological reasons I would like to limit the MINIMUM w/l
>of a MOS transistor to 3 or 4 (in some physical design rules
>of a process I have seen a minimal transistor width of 2).
>
>Do you think, from your experience, this would have a strong
>impact on the performance or the power consumption of a circuit?
>

Depends mostly on the Delta W for the target process or processes.
I've seen  2 micron processes with Delta W > 2, so if the transistor
was drawn 2 microns wide, you'd have nothing left! Also, as W
approaches Delta W, the characteristics really degrade.


-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)

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